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GateName.h
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7#ifndef CHIP_F69EDF9D_9F4F_4934_A0A7_1B6209076C7D
8#define CHIP_F69EDF9D_9F4F_4934_A0A7_1B6209076C7D
9
10/* ***************************************************************************************
11 * Include
12 */
13
14//----------------------------------------------------------------------------------------
15#include "mframe.h"
16
17//----------------------------------------------------------------------------------------
18
19/* ***************************************************************************************
20 * Namespace
21 */
22namespace chip::clock {
23 enum struct GateName : unsigned int;
24
25 const uint32 REG_PWM0SUBCTL = 250U;
26
27 inline uint32 getGateNameOffset(const GateName _this) {
28 return static_cast<uint32>(_this) >> 16;
29 }
30
31 inline uint32 getGateNameShift(const GateName _this) {
32 return static_cast<uint32>(_this) & 0x0000FFFFU;
33 }
34} // namespace chip::clock
35
36/* ***************************************************************************************
37 * Class/Interface/Struct/Enum
38 */
39enum struct chip::clock::GateName : unsigned int {
40 INPUTMUX0 = (0x00000U | (0U)),
41 INPUTMUX = (0x00000U | (0U)),
42 I3C0 = (0x00000U | (1U)),
43 CTIMER0 = (0x00000U | (2U)),
44 CTIMER1 = (0x00000U | (3U)),
45 CTIMER2 = (0x00000U | (4U)),
46 FREQME = (0x00000U | (5U)),
47 UTICK0 = (0x00000U | (6U)),
48 WWDT0 = (0x00000U | (7U)),
49 DMA = (0x00000U | (8U)),
50 AOI0 = (0x00000U | (9U)),
51 CRC = (0x00000U | (10U)),
52 CRC0 = (0x00000U | (10U)),
53 EIM = (0x00000U | (11U)),
54 ERM = (0x00000U | (12U)),
55 LPI2C0 = (0x00000U | (16U)),
56 LPSPI0 = (0x00000U | (17U)),
57 LPSPI1 = (0x00000U | (18U)),
58 LPUART0 = (0x00000U | (19U)),
59 LPUART1 = (0x00000U | (20U)),
60 LPUART2 = (0x00000U | (21U)),
61 USB0 = (0x00000U | (22U)),
62 QDC0 = (0x00000U | (23U)),
63 FLEXPWM0 = (0x00000U | (24U)),
64 OSTIMER0 = (0x00000U | (25U)),
65 ADC0 = (0x00000U | (26U)),
66 CMP0 = (0x00000U | (27U)),
67 CMP1 = (0x00000U | (28U)),
68 PORT0 = (0x00000U | (29U)),
69 PORT1 = (0x00000U | (30U)),
70 PORT2 = (0x00000U | (31U)),
71 PORT3 = ((0x10U << 16U) | (0U)),
72 ATX0 = ((0x10U << 16U) | (1U)),
73 MTR = ((0x10U << 16U) | (2U)),
74 TCU = ((0x10U << 16U) | (3U)),
75 EZRAMC_RAMA = ((0x10U << 16U) | (4U)),
76 GPIO0 = ((0x10U << 16U) | (5U)),
77 GPIO1 = ((0x10U << 16U) | (6U)),
78 GPIO2 = ((0x10U << 16U) | (7U)),
79 GPIO3 = ((0x10U << 16U) | (8U)),
80 ROMCP = ((0x10U << 16U) | (9U)),
81 PWMSM0 = ((REG_PWM0SUBCTL << 16U) | (0U)),
82 PWMSM1 = ((REG_PWM0SUBCTL << 16U) | (1U)),
83 PWMSM2 = ((REG_PWM0SUBCTL << 16U) | (2U)),
84 NOT_AVAIL = (0xFFFFFFFFU)
85};
86
87/* ***************************************************************************************
88 * End of file
89 */
90
91#endif /* CHIP_F69EDF9D_9F4F_4934_A0A7_1B6209076C7D */
chip::clock
Definition AttachID.h:23
chip::clock::GateName
GateName
Definition GateName.h:39