FMU.h

 
#ifndef CHIP_FAC9EE72_E5DD_4B9F_8A03_F08CED9C9083
#define CHIP_FAC9EE72_E5DD_4B9F_8A03_F08CED9C9083
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
#include "./../fmu/Mask.h"
#include "./../fmu/Register.h"
#include "./../fmu/Shift.h"
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::fmu {
  class FMU;
  extern Register& FMU0;
}  // namespace chip::fmu
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
class chip::fmu::FMU : public mframe::lang::Object {
  /* *************************************************************************************
   * Variable
   */
 
  /* *************************************************************************************
   * Abstract Method
   */
 
  /* *************************************************************************************
   * Construct Method
   */
 public:
  FMU(void);
 
  virtual ~FMU(void) override;
 
  /* *************************************************************************************
   * Operator Method
   */
 
  /* *************************************************************************************
   * Public Method <Override>
   */
 
  /* *************************************************************************************
   * Public Method
   */
 
  /* *************************************************************************************
   * Protected Method
   */
 
  /* *************************************************************************************
   * Private Method
   */
 
  /* *************************************************************************************
   * Static Variable
   */
 
  /* *************************************************************************************
   * Static Method
   */
 public:
  static inline constexpr uint32 FSTAT_FAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_FAIL) & +chip::fmu::Mask::FSTAT_FAIL);
  }
 
  static inline constexpr uint32 FSTAT_CMDABT(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_CMDABT) & +chip::fmu::Mask::FSTAT_CMDABT);
  }
 
  static inline constexpr uint32 FSTAT_PVIOL(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_PVIOL) & +chip::fmu::Mask::FSTAT_PVIOL);
  }
 
  static inline constexpr uint32 FSTAT_ACCERR(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_ACCERR) & +chip::fmu::Mask::FSTAT_ACCERR);
  }
 
  static inline constexpr uint32 FSTAT_CWSABT(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_CWSABT) & +chip::fmu::Mask::FSTAT_CWSABT);
  }
 
  static inline constexpr uint32 FSTAT_CCIF(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_CCIF) & +chip::fmu::Mask::FSTAT_CCIF);
  }
 
  static inline constexpr uint32 FSTAT_CMDPRT(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_CMDPRT) & +chip::fmu::Mask::FSTAT_CMDPRT);
  }
 
  static inline constexpr uint32 FSTAT_CMDP(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_CMDP) & +chip::fmu::Mask::FSTAT_CMDP);
  }
 
  static inline constexpr uint32 FSTAT_CMDDID(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_CMDDID) & +chip::fmu::Mask::FSTAT_CMDDID);
  }
 
  static inline constexpr uint32 FSTAT_DFDIF(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_DFDIF) & +chip::fmu::Mask::FSTAT_DFDIF);
  }
 
  static inline constexpr uint32 FSTAT_SALV_USED(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_SALV_USED) & +chip::fmu::Mask::FSTAT_SALV_USED);
  }
 
  static inline constexpr uint32 FSTAT_PEWEN(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_PEWEN) & +chip::fmu::Mask::FSTAT_PEWEN);
  }
 
  static inline constexpr uint32 FSTAT_PERDY(uint32 value) {
    return ((value << +chip::fmu::Shift::FSTAT_PERDY) & +chip::fmu::Mask::FSTAT_PERDY);
  }
 
  static inline constexpr uint32 FCNFG_CCIE(uint32 value) {
    return ((value << +chip::fmu::Shift::FCNFG_CCIE) & +chip::fmu::Mask::FCNFG_CCIE);
  }
 
  static inline constexpr uint32 FCNFG_ERSREQ(uint32 value) {
    return ((value << +chip::fmu::Shift::FCNFG_ERSREQ) & +chip::fmu::Mask::FCNFG_ERSREQ);
  }
 
  static inline constexpr uint32 FCNFG_DFDIE(uint32 value) {
    return ((value << +chip::fmu::Shift::FCNFG_DFDIE) & +chip::fmu::Mask::FCNFG_DFDIE);
  }
 
  static inline constexpr uint32 FCNFG_ERSIEN0(uint32 value) {
    return ((value << +chip::fmu::Shift::FCNFG_ERSIEN0) & +chip::fmu::Mask::FCNFG_ERSIEN0);
  }
 
  static inline constexpr uint32 FCNFG_ERSIEN1(uint32 value) {
    return ((value << +chip::fmu::Shift::FCNFG_ERSIEN1) & +chip::fmu::Mask::FCNFG_ERSIEN1);
  }
 
  static inline constexpr uint32 FCTRL_RWSC(uint32 value) {
    return ((value << +chip::fmu::Shift::FCTRL_RWSC) & +chip::fmu::Mask::FCTRL_RWSC);
  }
 
  static inline constexpr uint32 FCTRL_LSACTIVE(uint32 value) {
    return ((value << +chip::fmu::Shift::FCTRL_LSACTIVE) & +chip::fmu::Mask::FCTRL_LSACTIVE);
  }
 
  static inline constexpr uint32 FCTRL_FDFD(uint32 value) {
    return ((value << +chip::fmu::Shift::FCTRL_FDFD) & +chip::fmu::Mask::FCTRL_FDFD);
  }
 
  static inline constexpr uint32 FCTRL_ABTREQ(uint32 value) {
    return ((value << +chip::fmu::Shift::FCTRL_ABTREQ) & +chip::fmu::Mask::FCTRL_ABTREQ);
  }
 
  static inline constexpr uint32 FTEST_TMECTL(uint32 value) {
    return ((value << +chip::fmu::Shift::FTEST_TMECTL) & +chip::fmu::Mask::FTEST_TMECTL);
  }
 
  static inline constexpr uint32 FTEST_TMEWR(uint32 value) {
    return ((value << +chip::fmu::Shift::FTEST_TMEWR) & +chip::fmu::Mask::FTEST_TMEWR);
  }
 
  static inline constexpr uint32 FTEST_TME(uint32 value) {
    return ((value << +chip::fmu::Shift::FTEST_TME) & +chip::fmu::Mask::FTEST_TME);
  }
 
  static inline constexpr uint32 FTEST_TMODE(uint32 value) {
    return ((value << +chip::fmu::Shift::FTEST_TMODE) & +chip::fmu::Mask::FTEST_TMODE);
  }
 
  static inline constexpr uint32 FTEST_TMELOCK(uint32 value) {
    return ((value << +chip::fmu::Shift::FTEST_TMELOCK) & +chip::fmu::Mask::FTEST_TMELOCK);
  }
 
  static inline constexpr uint32 FCCOB0_CMDCODE(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB0_CMDCODE) & +chip::fmu::Mask::FCCOB0_CMDCODE);
  }
 
  static inline constexpr uint32 FCCOB1_CMDOPT(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB1_CMDOPT) & +chip::fmu::Mask::FCCOB1_CMDOPT);
  }
 
  static inline constexpr uint32 FCCOB2_CMDADDR(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB2_CMDADDR) & +chip::fmu::Mask::FCCOB2_CMDADDR);
  }
 
  static inline constexpr uint32 FCCOB3_CMDADDRE(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB3_CMDADDRE) & +chip::fmu::Mask::FCCOB3_CMDADDRE);
  }
 
  static inline constexpr uint32 FCCOB4_CMDDATA0(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB4_CMDDATA0) & +chip::fmu::Mask::FCCOB4_CMDDATA0);
  }
 
  static inline constexpr uint32 FCCOB5_CMDDATA1(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB5_CMDDATA1) & +chip::fmu::Mask::FCCOB5_CMDDATA1);
  }
 
  static inline constexpr uint32 FCCOB6_CMDDATA2(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB6_CMDDATA2) & +chip::fmu::Mask::FCCOB6_CMDDATA2);
  }
 
  static inline constexpr uint32 FCCOB7_CMDDATA3(uint32 value) {
    return ((value << +chip::fmu::Shift::FCCOB7_CMDDATA3) & +chip::fmu::Mask::FCCOB7_CMDDATA3);
  }
 
  static inline constexpr uint32 RESET_STATUS_ARY_TRIM_DONE(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_ARY_TRIM_DONE) & +chip::fmu::Mask::RESET_STATUS_ARY_TRIM_DONE);
  }
 
  static inline constexpr uint32 RESET_STATUS_FMU_PARM_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_FMU_PARM_EN) & +chip::fmu::Mask::RESET_STATUS_FMU_PARM_EN);
  }
 
  static inline constexpr uint32 RESET_STATUS_FMU_PARM_DONE(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_FMU_PARM_DONE) & +chip::fmu::Mask::RESET_STATUS_FMU_PARM_DONE);
  }
 
  static inline constexpr uint32 RESET_STATUS_SOC_TRIM_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_SOC_TRIM_EN) & +chip::fmu::Mask::RESET_STATUS_SOC_TRIM_EN);
  }
 
  static inline constexpr uint32 RESET_STATUS_SOC_TRIM_ECC(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_SOC_TRIM_ECC) & +chip::fmu::Mask::RESET_STATUS_SOC_TRIM_ECC);
  }
 
  static inline constexpr uint32 RESET_STATUS_SOC_TRIM_DONE(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_SOC_TRIM_DONE) & +chip::fmu::Mask::RESET_STATUS_SOC_TRIM_DONE);
  }
 
  static inline constexpr uint32 RESET_STATUS_RPR_DONE(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_RPR_DONE) & +chip::fmu::Mask::RESET_STATUS_RPR_DONE);
  }
 
  static inline constexpr uint32 RESET_STATUS_INIT_DONE(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_INIT_DONE) & +chip::fmu::Mask::RESET_STATUS_INIT_DONE);
  }
 
  static inline constexpr uint32 RESET_STATUS_RST_SF_ERR(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_RST_SF_ERR) & +chip::fmu::Mask::RESET_STATUS_RST_SF_ERR);
  }
 
  static inline constexpr uint32 RESET_STATUS_RST_DF_ERR(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_RST_DF_ERR) & +chip::fmu::Mask::RESET_STATUS_RST_DF_ERR);
  }
 
  static inline constexpr uint32 RESET_STATUS_SOC_TRIM_DF_ERR(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_SOC_TRIM_DF_ERR) & +chip::fmu::Mask::RESET_STATUS_SOC_TRIM_DF_ERR);
  }
 
  static inline constexpr uint32 RESET_STATUS_RST_PATCH_LD(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_RST_PATCH_LD) & +chip::fmu::Mask::RESET_STATUS_RST_PATCH_LD);
  }
 
  static inline constexpr uint32 RESET_STATUS_RECALL_DATA_MISMATCH(uint32 value) {
    return ((value << +chip::fmu::Shift::RESET_STATUS_RECALL_DATA_MISMATCH) & +chip::fmu::Mask::RESET_STATUS_RECALL_DATA_MISMATCH);
  }
 
  static inline constexpr uint32 MCTL_COREHLD(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_COREHLD) & +chip::fmu::Mask::MCTL_COREHLD);
  }
 
  static inline constexpr uint32 MCTL_LSACT_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_LSACT_EN) & +chip::fmu::Mask::MCTL_LSACT_EN);
  }
 
  static inline constexpr uint32 MCTL_LSACTWREN(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_LSACTWREN) & +chip::fmu::Mask::MCTL_LSACTWREN);
  }
 
  static inline constexpr uint32 MCTL_MASTER_REPAIR_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_MASTER_REPAIR_EN) & +chip::fmu::Mask::MCTL_MASTER_REPAIR_EN);
  }
 
  static inline constexpr uint32 MCTL_RFCMDEN(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_RFCMDEN) & +chip::fmu::Mask::MCTL_RFCMDEN);
  }
 
  static inline constexpr uint32 MCTL_CWSABTEN(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_CWSABTEN) & +chip::fmu::Mask::MCTL_CWSABTEN);
  }
 
  static inline constexpr uint32 MCTL_MRGRDDIS(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_MRGRDDIS) & +chip::fmu::Mask::MCTL_MRGRDDIS);
  }
 
  static inline constexpr uint32 MCTL_MRGRD0(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_MRGRD0) & +chip::fmu::Mask::MCTL_MRGRD0);
  }
 
  static inline constexpr uint32 MCTL_MRGRD1(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_MRGRD1) & +chip::fmu::Mask::MCTL_MRGRD1);
  }
 
  static inline constexpr uint32 MCTL_ERSAACK(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_ERSAACK) & +chip::fmu::Mask::MCTL_ERSAACK);
  }
 
  static inline constexpr uint32 MCTL_SCAN_OBS(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_SCAN_OBS) & +chip::fmu::Mask::MCTL_SCAN_OBS);
  }
 
  static inline constexpr uint32 MCTL_BIST_CTL(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_BIST_CTL) & +chip::fmu::Mask::MCTL_BIST_CTL);
  }
 
  static inline constexpr uint32 MCTL_SMWR_CTL(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_SMWR_CTL) & +chip::fmu::Mask::MCTL_SMWR_CTL);
  }
 
  static inline constexpr uint32 MCTL_SALV_DIS(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_SALV_DIS) & +chip::fmu::Mask::MCTL_SALV_DIS);
  }
 
  static inline constexpr uint32 MCTL_SOC_ECC_CTL(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_SOC_ECC_CTL) & +chip::fmu::Mask::MCTL_SOC_ECC_CTL);
  }
 
  static inline constexpr uint32 MCTL_FMU_ECC_CTL(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_FMU_ECC_CTL) & +chip::fmu::Mask::MCTL_FMU_ECC_CTL);
  }
 
  static inline constexpr uint32 MCTL_BIST_PWR_DIS(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_BIST_PWR_DIS) & +chip::fmu::Mask::MCTL_BIST_PWR_DIS);
  }
 
  static inline constexpr uint32 MCTL_OSC_H(uint32 value) {
    return ((value << +chip::fmu::Shift::MCTL_OSC_H) & +chip::fmu::Mask::MCTL_OSC_H);
  }
 
  static inline constexpr uint32 BSEL_GEN_SBSEL_GEN(uint32 value) {
    return ((value << +chip::fmu::Shift::BSEL_GEN_SBSEL_GEN) & +chip::fmu::Mask::BSEL_GEN_SBSEL_GEN);
  }
 
  static inline constexpr uint32 BSEL_GEN_MBSEL_GEN(uint32 value) {
    return ((value << +chip::fmu::Shift::BSEL_GEN_MBSEL_GEN) & +chip::fmu::Mask::BSEL_GEN_MBSEL_GEN);
  }
 
  static inline constexpr uint32 PWR_OPT_PD_CDIV(uint32 value) {
    return ((value << +chip::fmu::Shift::PWR_OPT_PD_CDIV) & +chip::fmu::Mask::PWR_OPT_PD_CDIV);
  }
 
  static inline constexpr uint32 PWR_OPT_SLM_COUNT(uint32 value) {
    return ((value << +chip::fmu::Shift::PWR_OPT_SLM_COUNT) & +chip::fmu::Mask::PWR_OPT_SLM_COUNT);
  }
 
  static inline constexpr uint32 PWR_OPT_PD_TIMER_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::PWR_OPT_PD_TIMER_EN) & +chip::fmu::Mask::PWR_OPT_PD_TIMER_EN);
  }
 
  static inline constexpr uint32 CMD_CHECK_ALIGNFAIL_PHR(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ALIGNFAIL_PHR) & +chip::fmu::Mask::CMD_CHECK_ALIGNFAIL_PHR);
  }
 
  static inline constexpr uint32 CMD_CHECK_ALIGNFAIL_PG(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ALIGNFAIL_PG) & +chip::fmu::Mask::CMD_CHECK_ALIGNFAIL_PG);
  }
 
  static inline constexpr uint32 CMD_CHECK_ALIGNFAIL_SCR(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ALIGNFAIL_SCR) & +chip::fmu::Mask::CMD_CHECK_ALIGNFAIL_SCR);
  }
 
  static inline constexpr uint32 CMD_CHECK_ALIGNFAIL_BLK(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ALIGNFAIL_BLK) & +chip::fmu::Mask::CMD_CHECK_ALIGNFAIL_BLK);
  }
 
  static inline constexpr uint32 CMD_CHECK_ADDR_FAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ADDR_FAIL) & +chip::fmu::Mask::CMD_CHECK_ADDR_FAIL);
  }
 
  static inline constexpr uint32 CMD_CHECK_IFR_CMD(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_IFR_CMD) & +chip::fmu::Mask::CMD_CHECK_IFR_CMD);
  }
 
  static inline constexpr uint32 CMD_CHECK_ALL_CMD(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ALL_CMD) & +chip::fmu::Mask::CMD_CHECK_ALL_CMD);
  }
 
  static inline constexpr uint32 CMD_CHECK_RANGE_FAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_RANGE_FAIL) & +chip::fmu::Mask::CMD_CHECK_RANGE_FAIL);
  }
 
  static inline constexpr uint32 CMD_CHECK_SCR_ALIGN_CHK(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_SCR_ALIGN_CHK) & +chip::fmu::Mask::CMD_CHECK_SCR_ALIGN_CHK);
  }
 
  static inline constexpr uint32 CMD_CHECK_OPTION_FAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_OPTION_FAIL) & +chip::fmu::Mask::CMD_CHECK_OPTION_FAIL);
  }
 
  static inline constexpr uint32 CMD_CHECK_ILLEGAL_CMD(uint32 value) {
    return ((value << +chip::fmu::Shift::CMD_CHECK_ILLEGAL_CMD) & +chip::fmu::Mask::CMD_CHECK_ILLEGAL_CMD);
  }
 
  static inline constexpr uint32 BSEL_SBSEL(uint32 value) {
    return ((value << +chip::fmu::Shift::BSEL_SBSEL) & +chip::fmu::Mask::BSEL_SBSEL);
  }
 
  static inline constexpr uint32 BSEL_MBSEL(uint32 value) {
    return ((value << +chip::fmu::Shift::BSEL_MBSEL) & +chip::fmu::Mask::BSEL_MBSEL);
  }
 
  static inline constexpr uint32 MSIZE_MAXADDR0(uint32 value) {
    return ((value << +chip::fmu::Shift::MSIZE_MAXADDR0) & +chip::fmu::Mask::MSIZE_MAXADDR0);
  }
 
  static inline constexpr uint32 FLASH_RD_ADD_FLASH_RD_ADD(uint32 value) {
    return ((value << +chip::fmu::Shift::FLASH_RD_ADD_FLASH_RD_ADD) & +chip::fmu::Mask::FLASH_RD_ADD_FLASH_RD_ADD);
  }
 
  static inline constexpr uint32 FLASH_STOP_ADD_FLASH_STOP_ADD(uint32 value) {
    return ((value << +chip::fmu::Shift::FLASH_STOP_ADD_FLASH_STOP_ADD) & +chip::fmu::Mask::FLASH_STOP_ADD_FLASH_STOP_ADD);
  }
 
  static inline constexpr uint32 FLASH_RD_CTRL_FLASH_RD(uint32 value) {
    return ((value << +chip::fmu::Shift::FLASH_RD_CTRL_FLASH_RD) & +chip::fmu::Mask::FLASH_RD_CTRL_FLASH_RD);
  }
 
  static inline constexpr uint32 FLASH_RD_CTRL_WIDE_LOAD(uint32 value) {
    return ((value << +chip::fmu::Shift::FLASH_RD_CTRL_WIDE_LOAD) & +chip::fmu::Mask::FLASH_RD_CTRL_WIDE_LOAD);
  }
 
  static inline constexpr uint32 FLASH_RD_CTRL_SINGLE_RD(uint32 value) {
    return ((value << +chip::fmu::Shift::FLASH_RD_CTRL_SINGLE_RD) & +chip::fmu::Mask::FLASH_RD_CTRL_SINGLE_RD);
  }
 
  static inline constexpr uint32 MM_ADDR_MM_ADDR(uint32 value) {
    return ((value << +chip::fmu::Shift::MM_ADDR_MM_ADDR) & +chip::fmu::Mask::MM_ADDR_MM_ADDR);
  }
 
  static inline constexpr uint32 MM_WDATA_MM_WDATA(uint32 value) {
    return ((value << +chip::fmu::Shift::MM_WDATA_MM_WDATA) & +chip::fmu::Mask::MM_WDATA_MM_WDATA);
  }
 
  static inline constexpr uint32 MM_CTL_MM_SEL(uint32 value) {
    return ((value << +chip::fmu::Shift::MM_CTL_MM_SEL) & +chip::fmu::Mask::MM_CTL_MM_SEL);
  }
 
  static inline constexpr uint32 MM_CTL_MM_RD(uint32 value) {
    return ((value << +chip::fmu::Shift::MM_CTL_MM_RD) & +chip::fmu::Mask::MM_CTL_MM_RD);
  }
 
  static inline constexpr uint32 MM_CTL_BIST_ON(uint32 value) {
    return ((value << +chip::fmu::Shift::MM_CTL_BIST_ON) & +chip::fmu::Mask::MM_CTL_BIST_ON);
  }
 
  static inline constexpr uint32 MM_CTL_FORCE_SW_CLK(uint32 value) {
    return ((value << +chip::fmu::Shift::MM_CTL_FORCE_SW_CLK) & +chip::fmu::Mask::MM_CTL_FORCE_SW_CLK);
  }
 
  static inline constexpr uint32 UINT_CTL_SET_FAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::UINT_CTL_SET_FAIL) & +chip::fmu::Mask::UINT_CTL_SET_FAIL);
  }
 
  static inline constexpr uint32 UINT_CTL_DBERR(uint32 value) {
    return ((value << +chip::fmu::Shift::UINT_CTL_DBERR) & +chip::fmu::Mask::UINT_CTL_DBERR);
  }
 
  static inline constexpr uint32 RD_DATA0_RD_DATA0(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_DATA0_RD_DATA0) & +chip::fmu::Mask::RD_DATA0_RD_DATA0);
  }
 
  static inline constexpr uint32 RD_DATA1_RD_DATA1(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_DATA1_RD_DATA1) & +chip::fmu::Mask::RD_DATA1_RD_DATA1);
  }
 
  static inline constexpr uint32 RD_DATA2_RD_DATA2(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_DATA2_RD_DATA2) & +chip::fmu::Mask::RD_DATA2_RD_DATA2);
  }
 
  static inline constexpr uint32 RD_DATA3_RD_DATA3(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_DATA3_RD_DATA3) & +chip::fmu::Mask::RD_DATA3_RD_DATA3);
  }
 
  static inline constexpr uint32 PARITY_PARITY(uint32 value) {
    return ((value << +chip::fmu::Shift::PARITY_PARITY) & +chip::fmu::Mask::PARITY_PARITY);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_RD_CAPT(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_RD_CAPT) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_RD_CAPT);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_SE_SIZE(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_SE_SIZE) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_SE_SIZE);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_ECC_ENABLEB(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_ECC_ENABLEB) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_ECC_ENABLEB);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_MISR_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_MISR_EN) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_MISR_EN);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_CPY_PAR_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_CPY_PAR_EN) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_CPY_PAR_EN);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_AD_SET(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_AD_SET) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_AD_SET);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_WR_PATH_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_WR_PATH_EN) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_WR_PATH_EN);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_DBERR_REG(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_DBERR_REG) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_DBERR_REG);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_SBERR_REG(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_SBERR_REG) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_SBERR_REG);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_CPY_PHRASE_EN) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_CPY_PHRASE_EN);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_BIST_ECC_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_BIST_ECC_EN) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_BIST_ECC_EN);
  }
 
  static inline constexpr uint32 RD_PATH_CTRL_STATUS_LAST_READ(uint32 value) {
    return ((value << +chip::fmu::Shift::RD_PATH_CTRL_STATUS_LAST_READ) & +chip::fmu::Mask::RD_PATH_CTRL_STATUS_LAST_READ);
  }
 
  static inline constexpr uint32 SMW_DIN0_SMW_DIN0(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_DIN0_SMW_DIN0) & +chip::fmu::Mask::SMW_DIN0_SMW_DIN0);
  }
 
  static inline constexpr uint32 SMW_DIN1_SMW_DIN1(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_DIN1_SMW_DIN1) & +chip::fmu::Mask::SMW_DIN1_SMW_DIN1);
  }
 
  static inline constexpr uint32 SMW_DIN2_SMW_DIN2(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_DIN2_SMW_DIN2) & +chip::fmu::Mask::SMW_DIN2_SMW_DIN2);
  }
 
  static inline constexpr uint32 SMW_DIN3_SMW_DIN3(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_DIN3_SMW_DIN3) & +chip::fmu::Mask::SMW_DIN3_SMW_DIN3);
  }
 
  static inline constexpr uint32 SMW_ADDR_SMW_ADDR(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_ADDR_SMW_ADDR) & +chip::fmu::Mask::SMW_ADDR_SMW_ADDR);
  }
 
  static inline constexpr uint32 SMW_CMD_WAIT_CMD(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_CMD_WAIT_CMD) & +chip::fmu::Mask::SMW_CMD_WAIT_CMD);
  }
 
  static inline constexpr uint32 SMW_CMD_WAIT_WAIT_EN(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_CMD_WAIT_WAIT_EN) & +chip::fmu::Mask::SMW_CMD_WAIT_WAIT_EN);
  }
 
  static inline constexpr uint32 SMW_CMD_WAIT_WAIT_AUTO_SET(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_CMD_WAIT_WAIT_AUTO_SET) & +chip::fmu::Mask::SMW_CMD_WAIT_WAIT_AUTO_SET);
  }
 
  static inline constexpr uint32 SMW_STATUS_SMW_ERR(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_STATUS_SMW_ERR) & +chip::fmu::Mask::SMW_STATUS_SMW_ERR);
  }
 
  static inline constexpr uint32 SMW_STATUS_SMW_BUSY(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_STATUS_SMW_BUSY) & +chip::fmu::Mask::SMW_STATUS_SMW_BUSY);
  }
 
  static inline constexpr uint32 SMW_STATUS_BIST_BUSY(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_STATUS_BIST_BUSY) & +chip::fmu::Mask::SMW_STATUS_BIST_BUSY);
  }
 
  static inline constexpr uint32 SOCTRIM0_0_TRIM0_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM0_0_TRIM0_0) & +chip::fmu::Mask::SOCTRIM0_0_TRIM0_0);
  }
 
  static inline constexpr uint32 SOCTRIM0_1_TRIM0_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM0_1_TRIM0_1) & +chip::fmu::Mask::SOCTRIM0_1_TRIM0_1);
  }
 
  static inline constexpr uint32 SOCTRIM0_2_TRIM0_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM0_2_TRIM0_2) & +chip::fmu::Mask::SOCTRIM0_2_TRIM0_2);
  }
 
  static inline constexpr uint32 SOCTRIM0_3_TRIM0_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM0_3_TRIM0_3) & +chip::fmu::Mask::SOCTRIM0_3_TRIM0_3);
  }
 
  static inline constexpr uint32 SOCTRIM1_0_TRIM1_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM1_0_TRIM1_0) & +chip::fmu::Mask::SOCTRIM1_0_TRIM1_0);
  }
 
  static inline constexpr uint32 SOCTRIM1_1_TRIM1_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM1_1_TRIM1_1) & +chip::fmu::Mask::SOCTRIM1_1_TRIM1_1);
  }
 
  static inline constexpr uint32 SOCTRIM1_2_TRIM1_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM1_2_TRIM1_2) & +chip::fmu::Mask::SOCTRIM1_2_TRIM1_2);
  }
 
  static inline constexpr uint32 SOCTRIM1_3_TRIM1_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM1_3_TRIM1_3) & +chip::fmu::Mask::SOCTRIM1_3_TRIM1_3);
  }
 
  static inline constexpr uint32 SOCTRIM2_0_TRIM2_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM2_0_TRIM2_0) & +chip::fmu::Mask::SOCTRIM2_0_TRIM2_0);
  }
 
  static inline constexpr uint32 SOCTRIM2_1_TRIM2_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM2_1_TRIM2_1) & +chip::fmu::Mask::SOCTRIM2_1_TRIM2_1);
  }
 
  static inline constexpr uint32 SOCTRIM2_2_TRIM2_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM2_2_TRIM2_2) & +chip::fmu::Mask::SOCTRIM2_2_TRIM2_2);
  }
 
  static inline constexpr uint32 SOCTRIM2_3_TRIM2_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM2_3_TRIM2_3) & +chip::fmu::Mask::SOCTRIM2_3_TRIM2_3);
  }
 
  static inline constexpr uint32 SOCTRIM3_0_TRIM3_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM3_0_TRIM3_0) & +chip::fmu::Mask::SOCTRIM3_0_TRIM3_0);
  }
 
  static inline constexpr uint32 SOCTRIM3_1_TRIM3_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM3_1_TRIM3_1) & +chip::fmu::Mask::SOCTRIM3_1_TRIM3_1);
  }
 
  static inline constexpr uint32 SOCTRIM3_2_TRIM3_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM3_2_TRIM3_2) & +chip::fmu::Mask::SOCTRIM3_2_TRIM3_2);
  }
 
  static inline constexpr uint32 SOCTRIM3_3_TRIM3_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM3_3_TRIM3_3) & +chip::fmu::Mask::SOCTRIM3_3_TRIM3_3);
  }
 
  static inline constexpr uint32 SOCTRIM4_0_TRIM4_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM4_0_TRIM4_0) & +chip::fmu::Mask::SOCTRIM4_0_TRIM4_0);
  }
 
  static inline constexpr uint32 SOCTRIM4_1_TRIM4_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM4_1_TRIM4_1) & +chip::fmu::Mask::SOCTRIM4_1_TRIM4_1);
  }
 
  static inline constexpr uint32 SOCTRIM4_2_TRIM4_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM4_2_TRIM4_2) & +chip::fmu::Mask::SOCTRIM4_2_TRIM4_2);
  }
 
  static inline constexpr uint32 SOCTRIM4_3_TRIM4_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM4_3_TRIM4_3) & +chip::fmu::Mask::SOCTRIM4_3_TRIM4_3);
  }
 
  static inline constexpr uint32 SOCTRIM5_0_TRIM5_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM5_0_TRIM5_0) & +chip::fmu::Mask::SOCTRIM5_0_TRIM5_0);
  }
 
  static inline constexpr uint32 SOCTRIM5_1_TRIM5_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM5_1_TRIM5_1) & +chip::fmu::Mask::SOCTRIM5_1_TRIM5_1);
  }
 
  static inline constexpr uint32 SOCTRIM5_2_TRIM5_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM5_2_TRIM5_2) & +chip::fmu::Mask::SOCTRIM5_2_TRIM5_2);
  }
 
  static inline constexpr uint32 SOCTRIM5_3_TRIM5_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM5_3_TRIM5_3) & +chip::fmu::Mask::SOCTRIM5_3_TRIM5_3);
  }
 
  static inline constexpr uint32 SOCTRIM6_0_TRIM6_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM6_0_TRIM6_0) & +chip::fmu::Mask::SOCTRIM6_0_TRIM6_0);
  }
 
  static inline constexpr uint32 SOCTRIM6_1_TRIM6_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM6_1_TRIM6_1) & +chip::fmu::Mask::SOCTRIM6_1_TRIM6_1);
  }
 
  static inline constexpr uint32 SOCTRIM6_2_TRIM6_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM6_2_TRIM6_2) & +chip::fmu::Mask::SOCTRIM6_2_TRIM6_2);
  }
 
  static inline constexpr uint32 SOCTRIM6_3_TRIM6_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM6_3_TRIM6_3) & +chip::fmu::Mask::SOCTRIM6_3_TRIM6_3);
  }
 
  static inline constexpr uint32 SOCTRIM7_0_TRIM7_0(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM7_0_TRIM7_0) & +chip::fmu::Mask::SOCTRIM7_0_TRIM7_0);
  }
 
  static inline constexpr uint32 SOCTRIM7_1_TRIM7_1(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM7_1_TRIM7_1) & +chip::fmu::Mask::SOCTRIM7_1_TRIM7_1);
  }
 
  static inline constexpr uint32 SOCTRIM7_2_TRIM7_2(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM7_2_TRIM7_2) & +chip::fmu::Mask::SOCTRIM7_2_TRIM7_2);
  }
 
  static inline constexpr uint32 SOCTRIM7_3_TRIM7_3(uint32 value) {
    return ((value << +chip::fmu::Shift::SOCTRIM7_3_TRIM7_3) & +chip::fmu::Mask::SOCTRIM7_3_TRIM7_3);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_IPSEL0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_IPSEL0) & +chip::fmu::Mask::R_IP_CONFIG_IPSEL0);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_IPSEL1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_IPSEL1) & +chip::fmu::Mask::R_IP_CONFIG_IPSEL1);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_BIST_CDIVL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_BIST_CDIVL) & +chip::fmu::Mask::R_IP_CONFIG_BIST_CDIVL);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_CDIVS(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_CDIVS) & +chip::fmu::Mask::R_IP_CONFIG_CDIVS);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_BIST_TVFY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_BIST_TVFY) & +chip::fmu::Mask::R_IP_CONFIG_BIST_TVFY);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_TSTCTL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_TSTCTL) & +chip::fmu::Mask::R_IP_CONFIG_TSTCTL);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_DBGCTL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_DBGCTL) & +chip::fmu::Mask::R_IP_CONFIG_DBGCTL);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_BIST_CLK_SEL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_BIST_CLK_SEL) & +chip::fmu::Mask::R_IP_CONFIG_BIST_CLK_SEL);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_SMWTST(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_SMWTST) & +chip::fmu::Mask::R_IP_CONFIG_SMWTST);
  }
 
  static inline constexpr uint32 R_IP_CONFIG_ECCEN(uint32 value) {
    return ((value << +chip::fmu::Shift::R_IP_CONFIG_ECCEN) & +chip::fmu::Mask::R_IP_CONFIG_ECCEN);
  }
 
  static inline constexpr uint32 R_TESTCODE_TESTCODE(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TESTCODE_TESTCODE) & +chip::fmu::Mask::R_TESTCODE_TESTCODE);
  }
 
  static inline constexpr uint32 R_DFT_CTRL_DFT_XADR(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DFT_CTRL_DFT_XADR) & +chip::fmu::Mask::R_DFT_CTRL_DFT_XADR);
  }
 
  static inline constexpr uint32 R_DFT_CTRL_DFT_YADR(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DFT_CTRL_DFT_YADR) & +chip::fmu::Mask::R_DFT_CTRL_DFT_YADR);
  }
 
  static inline constexpr uint32 R_DFT_CTRL_DFT_DATA(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DFT_CTRL_DFT_DATA) & +chip::fmu::Mask::R_DFT_CTRL_DFT_DATA);
  }
 
  static inline constexpr uint32 R_DFT_CTRL_CMP_MASK(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DFT_CTRL_CMP_MASK) & +chip::fmu::Mask::R_DFT_CTRL_CMP_MASK);
  }
 
  static inline constexpr uint32 R_DFT_CTRL_DFT_DATA_SRC(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DFT_CTRL_DFT_DATA_SRC) & +chip::fmu::Mask::R_DFT_CTRL_DFT_DATA_SRC);
  }
 
  static inline constexpr uint32 R_ADR_CTRL_GRPSEL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ADR_CTRL_GRPSEL) & +chip::fmu::Mask::R_ADR_CTRL_GRPSEL);
  }
 
  static inline constexpr uint32 R_ADR_CTRL_XADR(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ADR_CTRL_XADR) & +chip::fmu::Mask::R_ADR_CTRL_XADR);
  }
 
  static inline constexpr uint32 R_ADR_CTRL_YADR(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ADR_CTRL_YADR) & +chip::fmu::Mask::R_ADR_CTRL_YADR);
  }
 
  static inline constexpr uint32 R_ADR_CTRL_PROG_ATTR(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ADR_CTRL_PROG_ATTR) & +chip::fmu::Mask::R_ADR_CTRL_PROG_ATTR);
  }
 
  static inline constexpr uint32 R_DATA_CTRL0_DATA0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL0_DATA0) & +chip::fmu::Mask::R_DATA_CTRL0_DATA0);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_MAS1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_MAS1) & +chip::fmu::Mask::R_PIN_CTRL_MAS1);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_IFREN(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_IFREN) & +chip::fmu::Mask::R_PIN_CTRL_IFREN);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_IFREN1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_IFREN1) & +chip::fmu::Mask::R_PIN_CTRL_IFREN1);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_REDEN(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_REDEN) & +chip::fmu::Mask::R_PIN_CTRL_REDEN);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_LVE(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_LVE) & +chip::fmu::Mask::R_PIN_CTRL_LVE);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_PV(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_PV) & +chip::fmu::Mask::R_PIN_CTRL_PV);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_EV(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_EV) & +chip::fmu::Mask::R_PIN_CTRL_EV);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_WIPGM(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_WIPGM) & +chip::fmu::Mask::R_PIN_CTRL_WIPGM);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_WHV(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_WHV) & +chip::fmu::Mask::R_PIN_CTRL_WHV);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_WMV(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_WMV) & +chip::fmu::Mask::R_PIN_CTRL_WMV);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_XE(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_XE) & +chip::fmu::Mask::R_PIN_CTRL_XE);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_YE(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_YE) & +chip::fmu::Mask::R_PIN_CTRL_YE);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_SE(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_SE) & +chip::fmu::Mask::R_PIN_CTRL_SE);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_ERASE(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_ERASE) & +chip::fmu::Mask::R_PIN_CTRL_ERASE);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_PROG(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_PROG) & +chip::fmu::Mask::R_PIN_CTRL_PROG);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_NVSTR(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_NVSTR) & +chip::fmu::Mask::R_PIN_CTRL_NVSTR);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_SLM(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_SLM) & +chip::fmu::Mask::R_PIN_CTRL_SLM);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_RECALL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_RECALL) & +chip::fmu::Mask::R_PIN_CTRL_RECALL);
  }
 
  static inline constexpr uint32 R_PIN_CTRL_HEM(uint32 value) {
    return ((value << +chip::fmu::Shift::R_PIN_CTRL_HEM) & +chip::fmu::Mask::R_PIN_CTRL_HEM);
  }
 
  static inline constexpr uint32 R_CNT_LOOP_CTRL_LOOPCNT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_CNT_LOOP_CTRL_LOOPCNT) & +chip::fmu::Mask::R_CNT_LOOP_CTRL_LOOPCNT);
  }
 
  static inline constexpr uint32 R_CNT_LOOP_CTRL_LOOPOPT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_CNT_LOOP_CTRL_LOOPOPT) & +chip::fmu::Mask::R_CNT_LOOP_CTRL_LOOPOPT);
  }
 
  static inline constexpr uint32 R_CNT_LOOP_CTRL_LOOPUNIT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_CNT_LOOP_CTRL_LOOPUNIT) & +chip::fmu::Mask::R_CNT_LOOP_CTRL_LOOPUNIT);
  }
 
  static inline constexpr uint32 R_CNT_LOOP_CTRL_LOOPDLY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_CNT_LOOP_CTRL_LOOPDLY) & +chip::fmu::Mask::R_CNT_LOOP_CTRL_LOOPDLY);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TNVSUNIT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TNVSUNIT) & +chip::fmu::Mask::R_TIMER_CTRL_TNVSUNIT);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TNVSDLY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TNVSDLY) & +chip::fmu::Mask::R_TIMER_CTRL_TNVSDLY);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TNVHUNIT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TNVHUNIT) & +chip::fmu::Mask::R_TIMER_CTRL_TNVHUNIT);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TNVHDLY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TNVHDLY) & +chip::fmu::Mask::R_TIMER_CTRL_TNVHDLY);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TPGSUNIT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TPGSUNIT) & +chip::fmu::Mask::R_TIMER_CTRL_TPGSUNIT);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TPGSDLY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TPGSDLY) & +chip::fmu::Mask::R_TIMER_CTRL_TPGSDLY);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TRCVUNIT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TRCVUNIT) & +chip::fmu::Mask::R_TIMER_CTRL_TRCVUNIT);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TRCVDLY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TRCVDLY) & +chip::fmu::Mask::R_TIMER_CTRL_TRCVDLY);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TLVSUNIT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TLVSUNIT) & +chip::fmu::Mask::R_TIMER_CTRL_TLVSUNIT);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_TLVSDLY_L(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_TLVSDLY_L) & +chip::fmu::Mask::R_TIMER_CTRL_TLVSDLY_L);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_BUSY(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_BUSY) & +chip::fmu::Mask::R_TEST_CTRL_BUSY);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_DEBUG(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_DEBUG) & +chip::fmu::Mask::R_TEST_CTRL_DEBUG);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_STATUS0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_STATUS0) & +chip::fmu::Mask::R_TEST_CTRL_STATUS0);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_STATUS1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_STATUS1) & +chip::fmu::Mask::R_TEST_CTRL_STATUS1);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_DEBUGRUN(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_DEBUGRUN) & +chip::fmu::Mask::R_TEST_CTRL_DEBUGRUN);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_STARTRUN(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_STARTRUN) & +chip::fmu::Mask::R_TEST_CTRL_STARTRUN);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_CMDINDEX(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_CMDINDEX) & +chip::fmu::Mask::R_TEST_CTRL_CMDINDEX);
  }
 
  static inline constexpr uint32 R_TEST_CTRL_DISABLE_IP1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TEST_CTRL_DISABLE_IP1) & +chip::fmu::Mask::R_TEST_CTRL_DISABLE_IP1);
  }
 
  static inline constexpr uint32 R_ABORT_LOOP_ABORT_LOOP(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ABORT_LOOP_ABORT_LOOP) & +chip::fmu::Mask::R_ABORT_LOOP_ABORT_LOOP);
  }
 
  static inline constexpr uint32 R_ADR_QUERY_YADRFAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ADR_QUERY_YADRFAIL) & +chip::fmu::Mask::R_ADR_QUERY_YADRFAIL);
  }
 
  static inline constexpr uint32 R_ADR_QUERY_XADRFAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_ADR_QUERY_XADRFAIL) & +chip::fmu::Mask::R_ADR_QUERY_XADRFAIL);
  }
 
  static inline constexpr uint32 R_DOUT_QUERY0_DOUTFAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DOUT_QUERY0_DOUTFAIL) & +chip::fmu::Mask::R_DOUT_QUERY0_DOUTFAIL);
  }
 
  static inline constexpr uint32 R_SMW_QUERY_SMWLOOP(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMW_QUERY_SMWLOOP) & +chip::fmu::Mask::R_SMW_QUERY_SMWLOOP);
  }
 
  static inline constexpr uint32 R_SMW_QUERY_SMWLAST(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMW_QUERY_SMWLAST) & +chip::fmu::Mask::R_SMW_QUERY_SMWLAST);
  }
 
  static inline constexpr uint32 R_SMW_SETTING0_SMWPARM0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMW_SETTING0_SMWPARM0) & +chip::fmu::Mask::R_SMW_SETTING0_SMWPARM0);
  }
 
  static inline constexpr uint32 R_SMW_SETTING1_SMWPARM1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMW_SETTING1_SMWPARM1) & +chip::fmu::Mask::R_SMW_SETTING1_SMWPARM1);
  }
 
  static inline constexpr uint32 R_SMP_WHV0_SMPWHV0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMP_WHV0_SMPWHV0) & +chip::fmu::Mask::R_SMP_WHV0_SMPWHV0);
  }
 
  static inline constexpr uint32 R_SMP_WHV1_SMPWHV1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMP_WHV1_SMPWHV1) & +chip::fmu::Mask::R_SMP_WHV1_SMPWHV1);
  }
 
  static inline constexpr uint32 R_SME_WHV0_SMEWHV0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SME_WHV0_SMEWHV0) & +chip::fmu::Mask::R_SME_WHV0_SMEWHV0);
  }
 
  static inline constexpr uint32 R_SME_WHV1_SMEWHV1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SME_WHV1_SMEWHV1) & +chip::fmu::Mask::R_SME_WHV1_SMEWHV1);
  }
 
  static inline constexpr uint32 R_SMW_SETTING2_SMWPARM2(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMW_SETTING2_SMWPARM2) & +chip::fmu::Mask::R_SMW_SETTING2_SMWPARM2);
  }
 
  static inline constexpr uint32 R_D_MISR0_DATASIG0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_D_MISR0_DATASIG0) & +chip::fmu::Mask::R_D_MISR0_DATASIG0);
  }
 
  static inline constexpr uint32 R_A_MISR0_ADRSIG0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_A_MISR0_ADRSIG0) & +chip::fmu::Mask::R_A_MISR0_ADRSIG0);
  }
 
  static inline constexpr uint32 R_C_MISR0_CTRLSIG0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_C_MISR0_CTRLSIG0) & +chip::fmu::Mask::R_C_MISR0_CTRLSIG0);
  }
 
  static inline constexpr uint32 R_SMW_SETTING3_SMWPARM3(uint32 value) {
    return ((value << +chip::fmu::Shift::R_SMW_SETTING3_SMWPARM3) & +chip::fmu::Mask::R_SMW_SETTING3_SMWPARM3);
  }
 
  static inline constexpr uint32 R_DATA_CTRL1_DATA1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL1_DATA1) & +chip::fmu::Mask::R_DATA_CTRL1_DATA1);
  }
 
  static inline constexpr uint32 R_DATA_CTRL2_DATA2(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL2_DATA2) & +chip::fmu::Mask::R_DATA_CTRL2_DATA2);
  }
 
  static inline constexpr uint32 R_DATA_CTRL3_DATA3(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL3_DATA3) & +chip::fmu::Mask::R_DATA_CTRL3_DATA3);
  }
 
  static inline constexpr uint32 R_REPAIR0_0_RDIS0_0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR0_0_RDIS0_0) & +chip::fmu::Mask::R_REPAIR0_0_RDIS0_0);
  }
 
  static inline constexpr uint32 R_REPAIR0_0_RADR0_0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR0_0_RADR0_0) & +chip::fmu::Mask::R_REPAIR0_0_RADR0_0);
  }
 
  static inline constexpr uint32 R_REPAIR0_1_RDIS0_1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR0_1_RDIS0_1) & +chip::fmu::Mask::R_REPAIR0_1_RDIS0_1);
  }
 
  static inline constexpr uint32 R_REPAIR0_1_RADR0_1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR0_1_RADR0_1) & +chip::fmu::Mask::R_REPAIR0_1_RADR0_1);
  }
 
  static inline constexpr uint32 R_REPAIR1_0_RDIS1_0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR1_0_RDIS1_0) & +chip::fmu::Mask::R_REPAIR1_0_RDIS1_0);
  }
 
  static inline constexpr uint32 R_REPAIR1_0_RADR1_0(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR1_0_RADR1_0) & +chip::fmu::Mask::R_REPAIR1_0_RADR1_0);
  }
 
  static inline constexpr uint32 R_REPAIR1_1_RDIS1_1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR1_1_RDIS1_1) & +chip::fmu::Mask::R_REPAIR1_1_RDIS1_1);
  }
 
  static inline constexpr uint32 R_REPAIR1_1_RADR1_1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_REPAIR1_1_RADR1_1) & +chip::fmu::Mask::R_REPAIR1_1_RADR1_1);
  }
 
  static inline constexpr uint32 R_DATA_CTRL0_EX_DATA0X(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL0_EX_DATA0X) & +chip::fmu::Mask::R_DATA_CTRL0_EX_DATA0X);
  }
 
  static inline constexpr uint32 R_TIMER_CTRL_EX_TLVSDLY_H(uint32 value) {
    return ((value << +chip::fmu::Shift::R_TIMER_CTRL_EX_TLVSDLY_H) & +chip::fmu::Mask::R_TIMER_CTRL_EX_TLVSDLY_H);
  }
 
  static inline constexpr uint32 R_DOUT_QUERY1_DOUT(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DOUT_QUERY1_DOUT) & +chip::fmu::Mask::R_DOUT_QUERY1_DOUT);
  }
 
  static inline constexpr uint32 R_D_MISR1_DATASIG1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_D_MISR1_DATASIG1) & +chip::fmu::Mask::R_D_MISR1_DATASIG1);
  }
 
  static inline constexpr uint32 R_A_MISR1_ADRSIG1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_A_MISR1_ADRSIG1) & +chip::fmu::Mask::R_A_MISR1_ADRSIG1);
  }
 
  static inline constexpr uint32 R_C_MISR1_CTRLSIG1(uint32 value) {
    return ((value << +chip::fmu::Shift::R_C_MISR1_CTRLSIG1) & +chip::fmu::Mask::R_C_MISR1_CTRLSIG1);
  }
 
  static inline constexpr uint32 R_DATA_CTRL1_EX_DATA1X(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL1_EX_DATA1X) & +chip::fmu::Mask::R_DATA_CTRL1_EX_DATA1X);
  }
 
  static inline constexpr uint32 R_DATA_CTRL2_EX_DATA2X(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL2_EX_DATA2X) & +chip::fmu::Mask::R_DATA_CTRL2_EX_DATA2X);
  }
 
  static inline constexpr uint32 R_DATA_CTRL3_EX_DATA3X(uint32 value) {
    return ((value << +chip::fmu::Shift::R_DATA_CTRL3_EX_DATA3X) & +chip::fmu::Mask::R_DATA_CTRL3_EX_DATA3X);
  }
 
  static inline constexpr uint32 SMW_TIMER_OPTION_SMW_CDIVL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_TIMER_OPTION_SMW_CDIVL) & +chip::fmu::Mask::SMW_TIMER_OPTION_SMW_CDIVL);
  }
 
  static inline constexpr uint32 SMW_TIMER_OPTION_SMW_TVFY(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_TIMER_OPTION_SMW_TVFY) & +chip::fmu::Mask::SMW_TIMER_OPTION_SMW_TVFY);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION0_MV_INIT(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION0_MV_INIT) & +chip::fmu::Mask::SMW_SETTING_OPTION0_MV_INIT);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION0_MV_END(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION0_MV_END) & +chip::fmu::Mask::SMW_SETTING_OPTION0_MV_END);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION0_MV_MISC(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION0_MV_MISC) & +chip::fmu::Mask::SMW_SETTING_OPTION0_MV_MISC);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION0_IPGM_INIT(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION0_IPGM_INIT) & +chip::fmu::Mask::SMW_SETTING_OPTION0_IPGM_INIT);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION0_IPGM_END(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION0_IPGM_END) & +chip::fmu::Mask::SMW_SETTING_OPTION0_IPGM_END);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION0_IPGM_MISC(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION0_IPGM_MISC) & +chip::fmu::Mask::SMW_SETTING_OPTION0_IPGM_MISC);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_THVS_CTRL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_THVS_CTRL) & +chip::fmu::Mask::SMW_SETTING_OPTION2_THVS_CTRL);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_TRCV_CTRL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_TRCV_CTRL) & +chip::fmu::Mask::SMW_SETTING_OPTION2_TRCV_CTRL);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_XTRA_ERS(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_XTRA_ERS) & +chip::fmu::Mask::SMW_SETTING_OPTION2_XTRA_ERS);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_XTRA_PGM(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_XTRA_PGM) & +chip::fmu::Mask::SMW_SETTING_OPTION2_XTRA_PGM);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_WHV_CNTR(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_WHV_CNTR) & +chip::fmu::Mask::SMW_SETTING_OPTION2_WHV_CNTR);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_POST_TERS(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_POST_TERS) & +chip::fmu::Mask::SMW_SETTING_OPTION2_POST_TERS);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_POST_TPGM(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_POST_TPGM) & +chip::fmu::Mask::SMW_SETTING_OPTION2_POST_TPGM);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_VFY_OPT(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_VFY_OPT) & +chip::fmu::Mask::SMW_SETTING_OPTION2_VFY_OPT);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_TPGM_OPT(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_TPGM_OPT) & +chip::fmu::Mask::SMW_SETTING_OPTION2_TPGM_OPT);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_MASK0_OPT(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_MASK0_OPT) & +chip::fmu::Mask::SMW_SETTING_OPTION2_MASK0_OPT);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION2_DIS_PRER(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION2_DIS_PRER) & +chip::fmu::Mask::SMW_SETTING_OPTION2_DIS_PRER);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION3_HEM_WHV_CNTR(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION3_HEM_WHV_CNTR) & +chip::fmu::Mask::SMW_SETTING_OPTION3_HEM_WHV_CNTR);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION3_HEM_MAX_ERS(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION3_HEM_MAX_ERS) & +chip::fmu::Mask::SMW_SETTING_OPTION3_HEM_MAX_ERS);
  }
 
  static inline constexpr uint32 SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0) & +chip::fmu::Mask::SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0);
  }
 
  static inline constexpr uint32 SMW_SME_WHV_OPTION0_SME_WHV_OPT0(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SME_WHV_OPTION0_SME_WHV_OPT0) & +chip::fmu::Mask::SMW_SME_WHV_OPTION0_SME_WHV_OPT0);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_TERS_CTRL0(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_TERS_CTRL0) & +chip::fmu::Mask::SMW_SETTING_OPTION1_TERS_CTRL0);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_TPGM_CTRL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_TPGM_CTRL) & +chip::fmu::Mask::SMW_SETTING_OPTION1_TPGM_CTRL);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_TNVS_CTRL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_TNVS_CTRL) & +chip::fmu::Mask::SMW_SETTING_OPTION1_TNVS_CTRL);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_TNVH_CTRL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_TNVH_CTRL) & +chip::fmu::Mask::SMW_SETTING_OPTION1_TNVH_CTRL);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_TPGS_CTRL(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_TPGS_CTRL) & +chip::fmu::Mask::SMW_SETTING_OPTION1_TPGS_CTRL);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_MAX_ERASE(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_MAX_ERASE) & +chip::fmu::Mask::SMW_SETTING_OPTION1_MAX_ERASE);
  }
 
  static inline constexpr uint32 SMW_SETTING_OPTION1_MAX_PROG(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SETTING_OPTION1_MAX_PROG) & +chip::fmu::Mask::SMW_SETTING_OPTION1_MAX_PROG);
  }
 
  static inline constexpr uint32 SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1) & +chip::fmu::Mask::SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1);
  }
 
  static inline constexpr uint32 SMW_SME_WHV_OPTION1_SME_WHV_OPT1(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_SME_WHV_OPTION1_SME_WHV_OPT1) & +chip::fmu::Mask::SMW_SME_WHV_OPTION1_SME_WHV_OPT1);
  }
 
  static inline constexpr uint32 REPAIR0_0_RDIS0_0(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR0_0_RDIS0_0) & +chip::fmu::Mask::REPAIR0_0_RDIS0_0);
  }
 
  static inline constexpr uint32 REPAIR0_0_RADR0_0(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR0_0_RADR0_0) & +chip::fmu::Mask::REPAIR0_0_RADR0_0);
  }
 
  static inline constexpr uint32 REPAIR0_1_RDIS0_1(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR0_1_RDIS0_1) & +chip::fmu::Mask::REPAIR0_1_RDIS0_1);
  }
 
  static inline constexpr uint32 REPAIR0_1_RADR0_1(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR0_1_RADR0_1) & +chip::fmu::Mask::REPAIR0_1_RADR0_1);
  }
 
  static inline constexpr uint32 REPAIR1_0_RDIS1_0(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR1_0_RDIS1_0) & +chip::fmu::Mask::REPAIR1_0_RDIS1_0);
  }
 
  static inline constexpr uint32 REPAIR1_0_RADR1_0(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR1_0_RADR1_0) & +chip::fmu::Mask::REPAIR1_0_RADR1_0);
  }
 
  static inline constexpr uint32 REPAIR1_1_RDIS1_1(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR1_1_RDIS1_1) & +chip::fmu::Mask::REPAIR1_1_RDIS1_1);
  }
 
  static inline constexpr uint32 REPAIR1_1_RADR1_1(uint32 value) {
    return ((value << +chip::fmu::Shift::REPAIR1_1_RADR1_1) & +chip::fmu::Mask::REPAIR1_1_RADR1_1);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_SMW_ARRAY(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_SMW_ARRAY) & +chip::fmu::Mask::SMW_HB_SIGNALS_SMW_ARRAY);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_USER_IFREN1(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_USER_IFREN1) & +chip::fmu::Mask::SMW_HB_SIGNALS_USER_IFREN1);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_USER_PV(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_USER_PV) & +chip::fmu::Mask::SMW_HB_SIGNALS_USER_PV);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_USER_EV(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_USER_EV) & +chip::fmu::Mask::SMW_HB_SIGNALS_USER_EV);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_USER_IFREN(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_USER_IFREN) & +chip::fmu::Mask::SMW_HB_SIGNALS_USER_IFREN);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_USER_REDEN(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_USER_REDEN) & +chip::fmu::Mask::SMW_HB_SIGNALS_USER_REDEN);
  }
 
  static inline constexpr uint32 SMW_HB_SIGNALS_USER_HEM(uint32 value) {
    return ((value << +chip::fmu::Shift::SMW_HB_SIGNALS_USER_HEM) & +chip::fmu::Mask::SMW_HB_SIGNALS_USER_HEM);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_BIST_DONE(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_BIST_DONE) & +chip::fmu::Mask::BIST_DUMP_CTRL_BIST_DONE);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_BIST_FAIL(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_BIST_FAIL) & +chip::fmu::Mask::BIST_DUMP_CTRL_BIST_FAIL);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_DATADUMP(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_DATADUMP) & +chip::fmu::Mask::BIST_DUMP_CTRL_DATADUMP);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_DATADUMP_TRIG(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_DATADUMP_TRIG) & +chip::fmu::Mask::BIST_DUMP_CTRL_DATADUMP_TRIG);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_DATADUMP_PATT(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_DATADUMP_PATT) & +chip::fmu::Mask::BIST_DUMP_CTRL_DATADUMP_PATT);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_DATADUMP_MRGEN(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_DATADUMP_MRGEN) & +chip::fmu::Mask::BIST_DUMP_CTRL_DATADUMP_MRGEN);
  }
 
  static inline constexpr uint32 BIST_DUMP_CTRL_DATADUMP_MRGTYPE(uint32 value) {
    return ((value << +chip::fmu::Shift::BIST_DUMP_CTRL_DATADUMP_MRGTYPE) & +chip::fmu::Mask::BIST_DUMP_CTRL_DATADUMP_MRGTYPE);
  }
 
  static inline constexpr uint32 ATX_PIN_CTRL_TM_TO_ATX(uint32 value) {
    return ((value << +chip::fmu::Shift::ATX_PIN_CTRL_TM_TO_ATX) & +chip::fmu::Mask::ATX_PIN_CTRL_TM_TO_ATX);
  }
 
  static inline constexpr uint32 FAILCNT_FAILCNT(uint32 value) {
    return ((value << +chip::fmu::Shift::FAILCNT_FAILCNT) & +chip::fmu::Mask::FAILCNT_FAILCNT);
  }
 
  static inline constexpr uint32 PGM_PULSE_CNT0_PGM_CNT0(uint32 value) {
    return ((value << +chip::fmu::Shift::PGM_PULSE_CNT0_PGM_CNT0) & +chip::fmu::Mask::PGM_PULSE_CNT0_PGM_CNT0);
  }
 
  static inline constexpr uint32 PGM_PULSE_CNT1_PGM_CNT1(uint32 value) {
    return ((value << +chip::fmu::Shift::PGM_PULSE_CNT1_PGM_CNT1) & +chip::fmu::Mask::PGM_PULSE_CNT1_PGM_CNT1);
  }
 
  static inline constexpr uint32 ERS_PULSE_CNT_ERS_CNT0(uint32 value) {
    return ((value << +chip::fmu::Shift::ERS_PULSE_CNT_ERS_CNT0) & +chip::fmu::Mask::ERS_PULSE_CNT_ERS_CNT0);
  }
 
  static inline constexpr uint32 ERS_PULSE_CNT_ERS_CNT1(uint32 value) {
    return ((value << +chip::fmu::Shift::ERS_PULSE_CNT_ERS_CNT1) & +chip::fmu::Mask::ERS_PULSE_CNT_ERS_CNT1);
  }
 
  static inline constexpr uint32 MAX_PULSE_CNT_LAST_PCNT(uint32 value) {
    return ((value << +chip::fmu::Shift::MAX_PULSE_CNT_LAST_PCNT) & +chip::fmu::Mask::MAX_PULSE_CNT_LAST_PCNT);
  }
 
  static inline constexpr uint32 MAX_PULSE_CNT_MAX_ERS_CNT(uint32 value) {
    return ((value << +chip::fmu::Shift::MAX_PULSE_CNT_MAX_ERS_CNT) & +chip::fmu::Mask::MAX_PULSE_CNT_MAX_ERS_CNT);
  }
 
  static inline constexpr uint32 MAX_PULSE_CNT_MAX_PGM_CNT(uint32 value) {
    return ((value << +chip::fmu::Shift::MAX_PULSE_CNT_MAX_PGM_CNT) & +chip::fmu::Mask::MAX_PULSE_CNT_MAX_PGM_CNT);
  }
 
  static inline constexpr uint32 PORT_CTRL_BDONE_SEL(uint32 value) {
    return ((value << +chip::fmu::Shift::PORT_CTRL_BDONE_SEL) & +chip::fmu::Mask::PORT_CTRL_BDONE_SEL);
  }
 
  static inline constexpr uint32 PORT_CTRL_BSDO_SEL(uint32 value) {
    return ((value << +chip::fmu::Shift::PORT_CTRL_BSDO_SEL) & +chip::fmu::Mask::PORT_CTRL_BSDO_SEL);
  }
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_FAC9EE72_E5DD_4B9F_8A03_F08CED9C9083 */