mFrame
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Div.h
1
7#ifndef CHIP_EF0462BD_15BF_44BD_86EC_F5FB32C2FFF7
8#define CHIP_EF0462BD_15BF_44BD_86EC_F5FB32C2FFF7
9
10/* ***************************************************************************************
11 * Include
12 */
13
14//----------------------------------------------------------------------------------------
15#include "mframe.h"
16
17//----------------------------------------------------------------------------------------
18
19/* ***************************************************************************************
20 * Namespace
21 */
22namespace chip::clock {
23 enum struct Div : unsigned int;
24
25 constexpr unsigned int operator+(Div e) {
26 return static_cast<unsigned int>(e);
27 }
28} // namespace chip::clock
29
30/* ***************************************************************************************
31 * Class/Interface/Struct/Enum
32 */
33enum struct chip::clock::Div : unsigned int {
34 I3C0_FCLK = (0x0A4U),
35 CTIMER0 = (0x0ACU),
36 CTIMER1 = (0x0B4U),
37 CTIMER2 = (0x0BCU),
38 WWDT0 = (0x0C4U),
39 LPI2C0 = (0x0CCU),
40 LPSPI0 = (0x0D4U),
41 LPSPI1 = (0x0DCU),
42 LPUART0 = (0x0E4U),
43 LPUART1 = (0x0ECU),
44 LPUART2 = (0x0F4U),
45 LPTMR0 = (0x104U),
46 ADC0 = (0x114U),
47 CMP0_FUNC = (0x11CU),
48 CMP0_RR = (0x124U),
49 CMP1_FUNC = (0x12CU),
50 CMP1_RR = (0x134U),
51 TRACE = (0x13CU),
52 CLKOUT = (0x144U),
53 SYSTICK = (0x14CU),
54 FRO_HF_DIV = (0x154U),
55 SLOWCLK = (0x378U),
56 AHBCLK = (0x380U),
57 MAX = (0x380U)
58};
59
60/* ***************************************************************************************
61 * End of file
62 */
63
64#endif /* CHIP_EF0462BD_15BF_44BD_86EC_F5FB32C2FFF7 */
chip::clock
Definition AttachID.h:23
chip::clock::Div
Div
Definition Div.h:33