CTIMER.h

 
#ifndef CHIP_B8A77621_2EFC_460F_B812_3A6D133A9B04
#define CHIP_B8A77621_2EFC_460F_B812_3A6D133A9B04
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
#include "./Mask.h"
#include "./Register.h"
#include "./Shift.h"
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::ctimer {
  class CTIMER;
  extern Register       &CTIMER0;
  extern Register       &CTIMER1;
  extern Register       &CTIMER2;
  extern Register *const CTIMER[3];
}
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
class chip::ctimer::CTIMER : public mframe::lang::Object {
  /* *************************************************************************************
   * Variable
   */
 
  /* *************************************************************************************
   * Abstract Method
   */
 
  /* *************************************************************************************
   * Construct Method
   */
 public:
  CTIMER(void);
 
  virtual ~CTIMER(void) override;
 
  /* *************************************************************************************
   * Operator Method
   */
 
  /* *************************************************************************************
   * Public Method <Override>
   */
 
  /* *************************************************************************************
   * Public Method
   */
 
  /* *************************************************************************************
   * Protected Method
   */
 
  /* *************************************************************************************
   * Private Method
   */
 
  /* *************************************************************************************
   * Static Variable
   */
 
  /* *************************************************************************************
   * Static Method
   */
 public:
  static inline constexpr uint32 IR_MR0INT(uint32 value) {
    return ((value << +Shift::IR_MR0INT) & +Mask::IR_MR0INT);
  }
 
  static inline constexpr uint32 IR_MR1INT(uint32 value) {
    return ((value << +Shift::IR_MR1INT) & +Mask::IR_MR1INT);
  }
 
  static inline constexpr uint32 IR_MR2INT(uint32 value) {
    return ((value << +Shift::IR_MR2INT) & +Mask::IR_MR2INT);
  }
 
  static inline constexpr uint32 IR_MR3INT(uint32 value) {
    return ((value << +Shift::IR_MR3INT) & +Mask::IR_MR3INT);
  }
 
  static inline constexpr uint32 IR_CR0INT(uint32 value) {
    return ((value << +Shift::IR_CR0INT) & +Mask::IR_CR0INT);
  }
 
  static inline constexpr uint32 IR_CR1INT(uint32 value) {
    return ((value << +Shift::IR_CR1INT) & +Mask::IR_CR1INT);
  }
 
  static inline constexpr uint32 IR_CR2INT(uint32 value) {
    return ((value << +Shift::IR_CR2INT) & +Mask::IR_CR2INT);
  }
 
  static inline constexpr uint32 IR_CR3INT(uint32 value) {
    return ((value << +Shift::IR_CR3INT) & +Mask::IR_CR3INT);
  }
 
  static inline constexpr uint32 TCR_CEN(uint32 value) {
    return ((value << +Shift::TCR_CEN) & +Mask::TCR_CEN);
  }
 
  static inline constexpr uint32 TCR_CRST(uint32 value) {
    return ((value << +Shift::TCR_CRST) & +Mask::TCR_CRST);
  }
 
  static inline constexpr uint32 TCR_AGCEN(uint32 value) {
    return ((value << +Shift::TCR_AGCEN) & +Mask::TCR_AGCEN);
  }
 
  static inline constexpr uint32 TCR_ATCEN(uint32 value) {
    return ((value << +Shift::TCR_ATCEN) & +Mask::TCR_ATCEN);
  }
 
  static inline constexpr uint32 TC_TCVAL(uint32 value) {
    return ((value << +Shift::TC_TCVAL) & +Mask::TC_TCVAL);
  }
 
  static inline constexpr uint32 PR_PRVAL(uint32 value) {
    return ((value << +Shift::PR_PRVAL) & +Mask::PR_PRVAL);
  }
 
  static inline constexpr uint32 PC_PCVAL(uint32 value) {
    return ((value << +Shift::PC_PCVAL) & +Mask::PC_PCVAL);
  }
 
  static inline constexpr uint32 MCR_MR0I(uint32 value) {
    return ((value << +Shift::MCR_MR0I) & +Mask::MCR_MR0I);
  }
 
  static inline constexpr uint32 MCR_MR0R(uint32 value) {
    return ((value << +Shift::MCR_MR0R) & +Mask::MCR_MR0R);
  }
 
  static inline constexpr uint32 MCR_MR0S(uint32 value) {
    return ((value << +Shift::MCR_MR0S) & +Mask::MCR_MR0S);
  }
 
  static inline constexpr uint32 MCR_MR1I(uint32 value) {
    return ((value << +Shift::MCR_MR1I) & +Mask::MCR_MR1I);
  }
 
  static inline constexpr uint32 MCR_MR1R(uint32 value) {
    return ((value << +Shift::MCR_MR1R) & +Mask::MCR_MR1R);
  }
 
  static inline constexpr uint32 MCR_MR1S(uint32 value) {
    return ((value << +Shift::MCR_MR1S) & +Mask::MCR_MR1S);
  }
 
  static inline constexpr uint32 MCR_MR2I(uint32 value) {
    return ((value << +Shift::MCR_MR2I) & +Mask::MCR_MR2I);
  }
 
  static inline constexpr uint32 MCR_MR2R(uint32 value) {
    return ((value << +Shift::MCR_MR2R) & +Mask::MCR_MR2R);
  }
 
  static inline constexpr uint32 MCR_MR2S(uint32 value) {
    return ((value << +Shift::MCR_MR2S) & +Mask::MCR_MR2S);
  }
 
  static inline constexpr uint32 MCR_MR3I(uint32 value) {
    return ((value << +Shift::MCR_MR3I) & +Mask::MCR_MR3I);
  }
 
  static inline constexpr uint32 MCR_MR3R(uint32 value) {
    return ((value << +Shift::MCR_MR3R) & +Mask::MCR_MR3R);
  }
 
  static inline constexpr uint32 MCR_MR3S(uint32 value) {
    return ((value << +Shift::MCR_MR3S) & +Mask::MCR_MR3S);
  }
 
  static inline constexpr uint32 MCR_MR0RL(uint32 value) {
    return ((value << +Shift::MCR_MR0RL) & +Mask::MCR_MR0RL);
  }
 
  static inline constexpr uint32 MCR_MR1RL(uint32 value) {
    return ((value << +Shift::MCR_MR1RL) & +Mask::MCR_MR1RL);
  }
 
  static inline constexpr uint32 MCR_MR2RL(uint32 value) {
    return ((value << +Shift::MCR_MR2RL) & +Mask::MCR_MR2RL);
  }
 
  static inline constexpr uint32 MCR_MR3RL(uint32 value) {
    return ((value << +Shift::MCR_MR3RL) & +Mask::MCR_MR3RL);
  }
 
  static inline constexpr uint32 MR_MATCH(uint32 value) {
    return ((value << +Shift::MR_MATCH) & +Mask::MR_MATCH);
  }
 
  static inline constexpr uint32 CCR_CAP0RE(uint32 value) {
    return ((value << +Shift::CCR_CAP0RE) & +Mask::CCR_CAP0RE);
  }
 
  static inline constexpr uint32 CCR_CAP0FE(uint32 value) {
    return ((value << +Shift::CCR_CAP0FE) & +Mask::CCR_CAP0FE);
  }
 
  static inline constexpr uint32 CCR_CAP0I(uint32 value) {
    return ((value << +Shift::CCR_CAP0I) & +Mask::CCR_CAP0I);
  }
 
  static inline constexpr uint32 CCR_CAP1RE(uint32 value) {
    return ((value << +Shift::CCR_CAP1RE) & +Mask::CCR_CAP1RE);
  }
 
  static inline constexpr uint32 CCR_CAP1FE(uint32 value) {
    return ((value << +Shift::CCR_CAP1FE) & +Mask::CCR_CAP1FE);
  }
 
  static inline constexpr uint32 CCR_CAP1I(uint32 value) {
    return ((value << +Shift::CCR_CAP1I) & +Mask::CCR_CAP1I);
  }
 
  static inline constexpr uint32 CCR_CAP2RE(uint32 value) {
    return ((value << +Shift::CCR_CAP2RE) & +Mask::CCR_CAP2RE);
  }
 
  static inline constexpr uint32 CCR_CAP2FE(uint32 value) {
    return ((value << +Shift::CCR_CAP2FE) & +Mask::CCR_CAP2FE);
  }
 
  static inline constexpr uint32 CCR_CAP2I(uint32 value) {
    return ((value << +Shift::CCR_CAP2I) & +Mask::CCR_CAP2I);
  }
 
  static inline constexpr uint32 CCR_CAP3RE(uint32 value) {
    return ((value << +Shift::CCR_CAP3RE) & +Mask::CCR_CAP3RE);
  }
 
  static inline constexpr uint32 CCR_CAP3FE(uint32 value) {
    return ((value << +Shift::CCR_CAP3FE) & +Mask::CCR_CAP3FE);
  }
  
  static inline constexpr uint32 CCR_CAP3I(uint32 value) {
    return ((value << +Shift::CCR_CAP3I) & +Mask::CCR_CAP3I);
  }
 
  static inline constexpr uint32 CR_CAP(uint32 value) {
    return ((value << +Shift::CR_CAP) & +Mask::CR_CAP);
  }
 
  static inline constexpr uint32 EMR_EM0(uint32 value) {
    return ((value << +Shift::EMR_EM0) & +Mask::EMR_EM0);
  }
  static inline constexpr uint32 EMR_EM1(uint32 value) {
    return ((value << +Shift::EMR_EM1) & +Mask::EMR_EM1);
  }
  static inline constexpr uint32 EMR_EM2(uint32 value) {
    return ((value << +Shift::EMR_EM2) & +Mask::EMR_EM2);
  }
  static inline constexpr uint32 EMR_EM3(uint32 value) {
    return ((value << +Shift::EMR_EM3) & +Mask::EMR_EM3);
  }
  static inline constexpr uint32 EMR_EMC0(uint32 value) {
    return ((value << +Shift::EMR_EMC0) & +Mask::EMR_EMC0);
  }
 
  static inline constexpr uint32 EMR_EMC1(uint32 value) {
    return ((value << +Shift::EMR_EMC1) & +Mask::EMR_EMC1);
  }
 
  static inline constexpr uint32 EMR_EMC2(uint32 value) {
    return ((value << +Shift::EMR_EMC2) & +Mask::EMR_EMC2);
  }
 
  static inline constexpr uint32 EMR_EMC3(uint32 value) {
    return ((value << +Shift::EMR_EMC3) & +Mask::EMR_EMC3);
  }
 
  static inline constexpr uint32 CTCR_CTMODE(uint32 value) {
    return ((value << +Shift::CTCR_CTMODE) & +Mask::CTCR_CTMODE);
  }
 
  static inline constexpr uint32 CTCR_CINSEL(uint32 value) {
    return ((value << +Shift::CTCR_CINSEL) & +Mask::CTCR_CINSEL);
  }
 
  static inline constexpr uint32 CTCR_ENCC(uint32 value) {
    return ((value << +Shift::CTCR_ENCC) & +Mask::CTCR_ENCC);
  }
  
  static inline constexpr uint32 CTCR_SELCC(uint32 value) {
    return ((value << +Shift::CTCR_SELCC) & +Mask::CTCR_SELCC);
  }
 
  static inline constexpr uint32 PWMC_PWMEN0(uint32 value) {
    return ((value << +Shift::PWMC_PWMEN0) & +Mask::PWMC_PWMEN0);
  }
 
  static inline constexpr uint32 PWMC_PWMEN1(uint32 value) {
    return ((value << +Shift::PWMC_PWMEN1) & +Mask::PWMC_PWMEN1);
  }
  static inline constexpr uint32 PWMC_PWMEN2(uint32 value) {
    return ((value << +Shift::PWMC_PWMEN2) & +Mask::PWMC_PWMEN2);
  }
  static inline constexpr uint32 PWMC_PWMEN3(uint32 value) {
    return ((value << +Shift::PWMC_PWMEN3) & +Mask::PWMC_PWMEN3);
  }
 
  static inline constexpr uint32 MSR_MATCH_SHADOW(uint32 value) {
    return ((value << +Shift::MSR_MATCH_SHADOW) & +Mask::MSR_MATCH_SHADOW);
  }
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_B8A77621_2EFC_460F_B812_3A6D133A9B04 */