_attach_i_d_8h_source.html

#ifndef CHIP_533338E5_D3E9_4A18_ACA6_02A1E7AEDAA6

#define CHIP_533338E5_D3E9_4A18_ACA6_02A1E7AEDAA6


/* ***************************************************************************************

 * Include

 */


//----------------------------------------------------------------------------------------

#include "mframe.h"


//----------------------------------------------------------------------------------------

#include "./SelectName.h"


/* ***************************************************************************************

 * Namespace

 */


namespace chip::clock {

  enum struct AttachID : unsigned int;


  constexpr unsigned int operator+(AttachID e) {

    return static_cast<unsigned int>(e);

  }


  static inline constexpr SelectName attachToSelectName(AttachID attachID) {

    return static_cast<SelectName>(+attachID >> 16U);

  }


  static inline constexpr uint32 attachClockSelect(AttachID attachID) {

    return (+attachID & 0x0000FFFFU);

  }


  static inline constexpr unsigned int CLK_ATTACH_MUX(SelectName reg, uint32 sel) {

    return (+reg << 16) | sel;

  }

}  // namespace chip::clock


/* ***************************************************************************************

 * Class/Interface/Struct/Enum

 */


enum struct chip::clock::AttachID : unsigned int {

  CLK_IN_TO_MAIN_CLK  = CLK_ATTACH_MUX(SelectName::SCGSCS, 1U),

  FRO12M_TO_MAIN_CLK  = CLK_ATTACH_MUX(SelectName::SCGSCS, 2U),

  FRO_HF_TO_MAIN_CLK  = CLK_ATTACH_MUX(SelectName::SCGSCS, 3U),

  CLK_16K_TO_MAIN_CLK = CLK_ATTACH_MUX(SelectName::SCGSCS, 4U),

  NONE_TO_MAIN_CLK    = CLK_ATTACH_MUX(SelectName::SCGSCS, 7U),

  FRO12M_TO_I3C0FCLK     = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 0U),

  FRO_HF_DIV_TO_I3C0FCLK = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 2U),

  CLK_IN_TO_I3C0FCLK     = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 3U),

  CLK_1M_TO_I3C0FCLK     = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 5U),

  NONE_TO_I3C0FCLK       = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 7U),

  FRO12M_TO_CTIMER0  = CLK_ATTACH_MUX(SelectName::CTIMER0, 0U),

  FRO_HF_TO_CTIMER0  = CLK_ATTACH_MUX(SelectName::CTIMER0, 1U),

  CLK_IN_TO_CTIMER0  = CLK_ATTACH_MUX(SelectName::CTIMER0, 3U),

  CLK_16K_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 4U),

  CLK_1M_TO_CTIMER0  = CLK_ATTACH_MUX(SelectName::CTIMER0, 5U),

  NONE_TO_CTIMER0    = CLK_ATTACH_MUX(SelectName::CTIMER0, 7U),

  FRO12M_TO_CTIMER1  = CLK_ATTACH_MUX(SelectName::CTIMER1, 0U),

  FRO_HF_TO_CTIMER1  = CLK_ATTACH_MUX(SelectName::CTIMER1, 1U),

  CLK_IN_TO_CTIMER1  = CLK_ATTACH_MUX(SelectName::CTIMER1, 3U),

  CLK_16K_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 4U),

  CLK_1M_TO_CTIMER1  = CLK_ATTACH_MUX(SelectName::CTIMER1, 5U),

  NONE_TO_CTIMER1    = CLK_ATTACH_MUX(SelectName::CTIMER1, 7U),

  FRO12M_TO_CTIMER2  = CLK_ATTACH_MUX(SelectName::CTIMER2, 0U),

  FRO_HF_TO_CTIMER2  = CLK_ATTACH_MUX(SelectName::CTIMER2, 1U),

  CLK_IN_TO_CTIMER2  = CLK_ATTACH_MUX(SelectName::CTIMER2, 3U),

  CLK_16K_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 4U),

  CLK_1M_TO_CTIMER2  = CLK_ATTACH_MUX(SelectName::CTIMER2, 5U),

  NONE_TO_CTIMER2    = CLK_ATTACH_MUX(SelectName::CTIMER2, 7U),

  FRO12M_TO_LPI2C0     = CLK_ATTACH_MUX(SelectName::LPI2C0, 0U),

  FRO_HF_DIV_TO_LPI2C0 = CLK_ATTACH_MUX(SelectName::LPI2C0, 2U),

  CLK_IN_TO_LPI2C0     = CLK_ATTACH_MUX(SelectName::LPI2C0, 3U),

  CLK_1M_TO_LPI2C0     = CLK_ATTACH_MUX(SelectName::LPI2C0, 5U),

  NONE_TO_LPI2C0       = CLK_ATTACH_MUX(SelectName::LPI2C0, 7U),

  FRO12M_TO_LPSPI0     = CLK_ATTACH_MUX(SelectName::LPSPI0, 0U),

  FRO_HF_DIV_TO_LPSPI0 = CLK_ATTACH_MUX(SelectName::LPSPI0, 2U),

  CLK_IN_TO_LPSPI0     = CLK_ATTACH_MUX(SelectName::LPSPI0, 3U),

  CLK_1M_TO_LPSPI0     = CLK_ATTACH_MUX(SelectName::LPSPI0, 5U),

  NONE_TO_LPSPI0       = CLK_ATTACH_MUX(SelectName::LPSPI0, 7U),

  FRO12M_TO_LPSPI1     = CLK_ATTACH_MUX(SelectName::LPSPI1, 0U),

  FRO_HF_DIV_TO_LPSPI1 = CLK_ATTACH_MUX(SelectName::LPSPI1, 2U),

  CLK_IN_TO_LPSPI1     = CLK_ATTACH_MUX(SelectName::LPSPI1, 3U),

  CLK_1M_TO_LPSPI1     = CLK_ATTACH_MUX(SelectName::LPSPI1, 5U),

  NONE_TO_LPSPI1       = CLK_ATTACH_MUX(SelectName::LPSPI1, 7U),

  FRO12M_TO_LPUART0     = CLK_ATTACH_MUX(SelectName::LPUART0, 0U),

  FRO_HF_DIV_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 2U),

  CLK_IN_TO_LPUART0     = CLK_ATTACH_MUX(SelectName::LPUART0, 3U),

  CLK_16K_TO_LPUART0    = CLK_ATTACH_MUX(SelectName::LPUART0, 4U),

  CLK_1M_TO_LPUART0     = CLK_ATTACH_MUX(SelectName::LPUART0, 5U),

  NONE_TO_LPUART0       = CLK_ATTACH_MUX(SelectName::LPUART0, 7U),

  FRO12M_TO_LPUART1     = CLK_ATTACH_MUX(SelectName::LPUART1, 0U),

  FRO_HF_DIV_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 2U),

  CLK_IN_TO_LPUART1     = CLK_ATTACH_MUX(SelectName::LPUART1, 3U),

  CLK_16K_TO_LPUART1    = CLK_ATTACH_MUX(SelectName::LPUART1, 4U),

  CLK_1M_TO_LPUART1     = CLK_ATTACH_MUX(SelectName::LPUART1, 5U),

  NONE_TO_LPUART1       = CLK_ATTACH_MUX(SelectName::LPUART1, 7U),

  FRO12M_TO_LPUART2     = CLK_ATTACH_MUX(SelectName::LPUART2, 0U),

  FRO_HF_DIV_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 2U),

  CLK_IN_TO_LPUART2     = CLK_ATTACH_MUX(SelectName::LPUART2, 3U),

  CLK_16K_TO_LPUART2    = CLK_ATTACH_MUX(SelectName::LPUART2, 4U),

  CLK_1M_TO_LPUART2     = CLK_ATTACH_MUX(SelectName::LPUART2, 5U),

  NONE_TO_LPUART2       = CLK_ATTACH_MUX(SelectName::LPUART2, 7U),

  CLK_48M_TO_USB0 = CLK_ATTACH_MUX(SelectName::USB0, 1U),

  CLK_IN_TO_USB0  = CLK_ATTACH_MUX(SelectName::USB0, 2U),

  NONE_TO_USB0    = CLK_ATTACH_MUX(SelectName::USB0, 3U),

  FRO12M_TO_LPTMR0     = CLK_ATTACH_MUX(SelectName::LPTMR0, 0U),

  FRO_HF_DIV_TO_LPTMR0 = CLK_ATTACH_MUX(SelectName::LPTMR0, 2U),

  CLK_IN_TO_LPTMR0     = CLK_ATTACH_MUX(SelectName::LPTMR0, 3U),

  CLK_1M_TO_LPTMR0     = CLK_ATTACH_MUX(SelectName::LPTMR0, 5U),

  NONE_TO_LPTMR0       = CLK_ATTACH_MUX(SelectName::LPTMR0, 7U),

  CLK_16K_TO_OSTIMER = CLK_ATTACH_MUX(SelectName::OSTIMER0, 0U),

  CLK_1M_TO_OSTIMER  = CLK_ATTACH_MUX(SelectName::OSTIMER0, 2U),

  NONE_TO_OSTIMER    = CLK_ATTACH_MUX(SelectName::OSTIMER0, 3U),

  FRO12M_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 0U),

  FRO_HF_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 1U),

  CLK_IN_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 3U),

  CLK_1M_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 5U),

  NONE_TO_ADC0   = CLK_ATTACH_MUX(SelectName::ADC0, 7U),

  FRO12M_TO_CMP0     = CLK_ATTACH_MUX(SelectName::CMP0_RR, 0U),

  FRO_HF_DIV_TO_CMP0 = CLK_ATTACH_MUX(SelectName::CMP0_RR, 2U),

  CLK_IN_TO_CMP0     = CLK_ATTACH_MUX(SelectName::CMP0_RR, 3U),

  CLK_1M_TO_CMP0     = CLK_ATTACH_MUX(SelectName::CMP0_RR, 5U),

  NONE_TO_CMP0       = CLK_ATTACH_MUX(SelectName::CMP0_RR, 7U),

  FRO12M_TO_CMP1     = CLK_ATTACH_MUX(SelectName::CMP1_RR, 0U),

  FRO_HF_DIV_TO_CMP1 = CLK_ATTACH_MUX(SelectName::CMP1_RR, 2U),

  CLK_IN_TO_CMP1     = CLK_ATTACH_MUX(SelectName::CMP1_RR, 3U),

  CLK_1M_TO_CMP1     = CLK_ATTACH_MUX(SelectName::CMP1_RR, 5U),

  NONE_TO_CMP1       = CLK_ATTACH_MUX(SelectName::CMP1_RR, 7U),

  CPU_CLK_TO_TRACE = CLK_ATTACH_MUX(SelectName::TRACE, 0U),

  CLK_1M_TO_TRACE  = CLK_ATTACH_MUX(SelectName::TRACE, 1U),

  CLK_16K_TO_TRACE = CLK_ATTACH_MUX(SelectName::TRACE, 2U),

  NONE_TO_TRACE    = CLK_ATTACH_MUX(SelectName::TRACE, 3U),

  FRO12M_TO_CLKOUT     = CLK_ATTACH_MUX(SelectName::CLKOUT, 0U),

  FRO_HF_DIV_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 1U),

  CLK_IN_TO_CLKOUT     = CLK_ATTACH_MUX(SelectName::CLKOUT, 2U),

  CLK_16K_TO_CLKOUT    = CLK_ATTACH_MUX(SelectName::CLKOUT, 3U),

  SLOW_CLK_TO_CLKOUT   = CLK_ATTACH_MUX(SelectName::CLKOUT, 6U),

  NONE_TO_CLKOUT       = CLK_ATTACH_MUX(SelectName::CLKOUT, 7U),

  CPU_CLK_TO_SYSTICK = CLK_ATTACH_MUX(SelectName::SYSTICK, 0U),

  CLK_1M_TO_SYSTICK  = CLK_ATTACH_MUX(SelectName::SYSTICK, 1U),

  CLK_16K_TO_SYSTICK = CLK_ATTACH_MUX(SelectName::SYSTICK, 2U),

  NONE_TO_SYSTICK    = CLK_ATTACH_MUX(SelectName::SYSTICK, 3U),

  NONE_TO_NONE = (0xFFFFFFFFU)

};


/* ***************************************************************************************

 * End of file

 */


#endif /* CHIP_533338E5_D3E9_4A18_ACA6_02A1E7AEDAA6 */

chip::clock
Definition AttachID.h:23

chip::clock::SelectName
SelectName
Definition SelectName.h:33

chip::clock::AttachID
AttachID
Definition AttachID.h:46

chip::clock::AttachID::NONE_TO_USB0
@ NONE_TO_USB0

chip::clock::AttachID::CLK_IN_TO_LPI2C0
@ CLK_IN_TO_LPI2C0

chip::clock::AttachID::CLK_IN_TO_LPSPI0
@ CLK_IN_TO_LPSPI0

chip::clock::AttachID::NONE_TO_LPUART1
@ NONE_TO_LPUART1

chip::clock::AttachID::FRO12M_TO_ADC0
@ FRO12M_TO_ADC0

chip::clock::AttachID::CLK_IN_TO_CTIMER1
@ CLK_IN_TO_CTIMER1

chip::clock::AttachID::CLK_IN_TO_CTIMER2
@ CLK_IN_TO_CTIMER2

chip::clock::AttachID::CLK_1M_TO_LPSPI0
@ CLK_1M_TO_LPSPI0

chip::clock::AttachID::FRO12M_TO_CTIMER1
@ FRO12M_TO_CTIMER1

chip::clock::AttachID::NONE_TO_NONE
@ NONE_TO_NONE

chip::clock::AttachID::CLK_1M_TO_TRACE
@ CLK_1M_TO_TRACE

chip::clock::AttachID::FRO_HF_DIV_TO_LPUART1
@ FRO_HF_DIV_TO_LPUART1

chip::clock::AttachID::FRO_HF_DIV_TO_CMP0
@ FRO_HF_DIV_TO_CMP0

chip::clock::AttachID::NONE_TO_CMP1
@ NONE_TO_CMP1

chip::clock::AttachID::CLK_1M_TO_CMP0
@ CLK_1M_TO_CMP0

chip::clock::AttachID::NONE_TO_CTIMER2
@ NONE_TO_CTIMER2

chip::clock::AttachID::CLK_1M_TO_LPI2C0
@ CLK_1M_TO_LPI2C0

chip::clock::AttachID::FRO12M_TO_LPSPI1
@ FRO12M_TO_LPSPI1

chip::clock::AttachID::CLK_IN_TO_CMP1
@ CLK_IN_TO_CMP1

chip::clock::AttachID::CLK_1M_TO_ADC0
@ CLK_1M_TO_ADC0

chip::clock::AttachID::CLK_IN_TO_LPUART0
@ CLK_IN_TO_LPUART0

chip::clock::AttachID::NONE_TO_OSTIMER
@ NONE_TO_OSTIMER

chip::clock::AttachID::CPU_CLK_TO_TRACE
@ CPU_CLK_TO_TRACE

chip::clock::AttachID::FRO_HF_DIV_TO_CMP1
@ FRO_HF_DIV_TO_CMP1

chip::clock::AttachID::CLK_16K_TO_SYSTICK
@ CLK_16K_TO_SYSTICK

chip::clock::AttachID::CLK_16K_TO_MAIN_CLK
@ CLK_16K_TO_MAIN_CLK

chip::clock::AttachID::CLK_16K_TO_OSTIMER
@ CLK_16K_TO_OSTIMER

chip::clock::AttachID::CLK_IN_TO_LPUART2
@ CLK_IN_TO_LPUART2

chip::clock::AttachID::FRO_HF_TO_ADC0
@ FRO_HF_TO_ADC0

chip::clock::AttachID::CLK_1M_TO_LPUART1
@ CLK_1M_TO_LPUART1

chip::clock::AttachID::FRO12M_TO_CMP1
@ FRO12M_TO_CMP1

chip::clock::AttachID::NONE_TO_CTIMER1
@ NONE_TO_CTIMER1

chip::clock::AttachID::CLK_IN_TO_LPUART1
@ CLK_IN_TO_LPUART1

chip::clock::AttachID::FRO_HF_TO_CTIMER0
@ FRO_HF_TO_CTIMER0

chip::clock::AttachID::FRO12M_TO_LPUART1
@ FRO12M_TO_LPUART1

chip::clock::AttachID::CLK_1M_TO_OSTIMER
@ CLK_1M_TO_OSTIMER

chip::clock::AttachID::FRO12M_TO_LPTMR0
@ FRO12M_TO_LPTMR0

chip::clock::AttachID::CLK_IN_TO_CTIMER0
@ CLK_IN_TO_CTIMER0

chip::clock::AttachID::FRO12M_TO_CTIMER2
@ FRO12M_TO_CTIMER2

chip::clock::AttachID::NONE_TO_CLKOUT
@ NONE_TO_CLKOUT

chip::clock::AttachID::CLK_IN_TO_CLKOUT
@ CLK_IN_TO_CLKOUT

chip::clock::AttachID::FRO_HF_TO_CTIMER2
@ FRO_HF_TO_CTIMER2

chip::clock::AttachID::CLK_IN_TO_ADC0
@ CLK_IN_TO_ADC0

chip::clock::AttachID::FRO12M_TO_I3C0FCLK
@ FRO12M_TO_I3C0FCLK

chip::clock::AttachID::NONE_TO_LPSPI1
@ NONE_TO_LPSPI1

chip::clock::AttachID::NONE_TO_LPUART2
@ NONE_TO_LPUART2

chip::clock::AttachID::CLK_1M_TO_LPSPI1
@ CLK_1M_TO_LPSPI1

chip::clock::AttachID::CLK_1M_TO_SYSTICK
@ CLK_1M_TO_SYSTICK

chip::clock::AttachID::CLK_16K_TO_CLKOUT
@ CLK_16K_TO_CLKOUT

chip::clock::AttachID::CLK_IN_TO_LPTMR0
@ CLK_IN_TO_LPTMR0

chip::clock::AttachID::CLK_1M_TO_CMP1
@ CLK_1M_TO_CMP1

chip::clock::AttachID::CLK_16K_TO_CTIMER1
@ CLK_16K_TO_CTIMER1

chip::clock::AttachID::CLK_48M_TO_USB0
@ CLK_48M_TO_USB0

chip::clock::AttachID::CLK_1M_TO_CTIMER1
@ CLK_1M_TO_CTIMER1

chip::clock::AttachID::FRO12M_TO_LPI2C0
@ FRO12M_TO_LPI2C0

chip::clock::AttachID::CPU_CLK_TO_SYSTICK
@ CPU_CLK_TO_SYSTICK

chip::clock::AttachID::NONE_TO_LPI2C0
@ NONE_TO_LPI2C0

chip::clock::AttachID::FRO12M_TO_CMP0
@ FRO12M_TO_CMP0

chip::clock::AttachID::CLK_IN_TO_CMP0
@ CLK_IN_TO_CMP0

chip::clock::AttachID::NONE_TO_LPUART0
@ NONE_TO_LPUART0

chip::clock::AttachID::FRO12M_TO_MAIN_CLK
@ FRO12M_TO_MAIN_CLK

chip::clock::AttachID::NONE_TO_TRACE
@ NONE_TO_TRACE

chip::clock::AttachID::FRO_HF_DIV_TO_I3C0FCLK
@ FRO_HF_DIV_TO_I3C0FCLK

chip::clock::AttachID::FRO_HF_DIV_TO_LPTMR0
@ FRO_HF_DIV_TO_LPTMR0

chip::clock::AttachID::CLK_1M_TO_I3C0FCLK
@ CLK_1M_TO_I3C0FCLK

chip::clock::AttachID::FRO_HF_DIV_TO_CLKOUT
@ FRO_HF_DIV_TO_CLKOUT

chip::clock::AttachID::FRO12M_TO_LPUART0
@ FRO12M_TO_LPUART0

chip::clock::AttachID::CLK_16K_TO_LPUART2
@ CLK_16K_TO_LPUART2

chip::clock::AttachID::FRO_HF_TO_MAIN_CLK
@ FRO_HF_TO_MAIN_CLK

chip::clock::AttachID::NONE_TO_LPSPI0
@ NONE_TO_LPSPI0

chip::clock::AttachID::NONE_TO_SYSTICK
@ NONE_TO_SYSTICK

chip::clock::AttachID::NONE_TO_CMP0
@ NONE_TO_CMP0

chip::clock::AttachID::NONE_TO_I3C0FCLK
@ NONE_TO_I3C0FCLK

chip::clock::AttachID::FRO12M_TO_CTIMER0
@ FRO12M_TO_CTIMER0

chip::clock::AttachID::NONE_TO_ADC0
@ NONE_TO_ADC0

chip::clock::AttachID::FRO_HF_DIV_TO_LPSPI0
@ FRO_HF_DIV_TO_LPSPI0

chip::clock::AttachID::FRO_HF_DIV_TO_LPSPI1
@ FRO_HF_DIV_TO_LPSPI1

chip::clock::AttachID::CLK_16K_TO_LPUART0
@ CLK_16K_TO_LPUART0

chip::clock::AttachID::NONE_TO_CTIMER0
@ NONE_TO_CTIMER0

chip::clock::AttachID::CLK_1M_TO_CTIMER2
@ CLK_1M_TO_CTIMER2

chip::clock::AttachID::FRO12M_TO_CLKOUT
@ FRO12M_TO_CLKOUT

chip::clock::AttachID::CLK_16K_TO_CTIMER2
@ CLK_16K_TO_CTIMER2

chip::clock::AttachID::FRO12M_TO_LPUART2
@ FRO12M_TO_LPUART2

chip::clock::AttachID::NONE_TO_MAIN_CLK
@ NONE_TO_MAIN_CLK

chip::clock::AttachID::FRO_HF_TO_CTIMER1
@ FRO_HF_TO_CTIMER1

chip::clock::AttachID::CLK_IN_TO_USB0
@ CLK_IN_TO_USB0

chip::clock::AttachID::CLK_1M_TO_CTIMER0
@ CLK_1M_TO_CTIMER0

chip::clock::AttachID::FRO_HF_DIV_TO_LPI2C0
@ FRO_HF_DIV_TO_LPI2C0

chip::clock::AttachID::CLK_16K_TO_CTIMER0
@ CLK_16K_TO_CTIMER0

chip::clock::AttachID::CLK_IN_TO_LPSPI1
@ CLK_IN_TO_LPSPI1

chip::clock::AttachID::CLK_1M_TO_LPTMR0
@ CLK_1M_TO_LPTMR0

chip::clock::AttachID::FRO_HF_DIV_TO_LPUART0
@ FRO_HF_DIV_TO_LPUART0

chip::clock::AttachID::CLK_IN_TO_MAIN_CLK
@ CLK_IN_TO_MAIN_CLK

chip::clock::AttachID::CLK_IN_TO_I3C0FCLK
@ CLK_IN_TO_I3C0FCLK

chip::clock::AttachID::CLK_16K_TO_LPUART1
@ CLK_16K_TO_LPUART1

chip::clock::AttachID::CLK_16K_TO_TRACE
@ CLK_16K_TO_TRACE

chip::clock::AttachID::SLOW_CLK_TO_CLKOUT
@ SLOW_CLK_TO_CLKOUT

chip::clock::AttachID::NONE_TO_LPTMR0
@ NONE_TO_LPTMR0

chip::clock::AttachID::FRO12M_TO_LPSPI0
@ FRO12M_TO_LPSPI0

chip::clock::AttachID::FRO_HF_DIV_TO_LPUART2
@ FRO_HF_DIV_TO_LPUART2

chip::clock::AttachID::CLK_1M_TO_LPUART0
@ CLK_1M_TO_LPUART0

chip::clock::AttachID::CLK_1M_TO_LPUART2
@ CLK_1M_TO_LPUART2