trdc/Mask.h

 
#ifndef CHIP_4B503756_C9BF_4641_86B8_961ABEA7AB89
#define CHIP_4B503756_C9BF_4641_86B8_961ABEA7AB89
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::trdc {
  enum struct Mask : unsigned int;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::trdc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct chip::trdc::Mask : unsigned int {
 
  MEM_GLBCFG_NBLKS = 0x000003FFU,
 
  MEM_GLBCFG_SIZE_LOG2 = 0x001F0000U,
 
  MEM_GLBCFG_CLRE = 0xC0000000U,
 
  MEMN_GLBAC_NUX = 0x00000001U,
 
  MEMN_GLBAC_NUW = 0x00000002U,
 
  MEMN_GLBAC_NUR = 0x00000004U,
 
  MEMN_GLBAC_NPX = 0x00000010U,
 
  MEMN_GLBAC_NPW = 0x00000020U,
 
  MEMN_GLBAC_NPR = 0x00000040U,
 
  MEMN_GLBAC_SUX = 0x00000100U,
 
  MEMN_GLBAC_SUW = 0x00000200U,
 
  MEMN_GLBAC_SUR = 0x00000400U,
 
  MEMN_GLBAC_SPX = 0x00001000U,
 
  MEMN_GLBAC_SPW = 0x00002000U,
 
  MEMN_GLBAC_SPR = 0x00004000U,
 
  MEMN_GLBAC_LK = 0x80000000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0 = 0x00000007U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0 = 0x00000008U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1 = 0x00000070U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1 = 0x00000080U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2 = 0x00000700U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2 = 0x00000800U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3 = 0x00007000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3 = 0x00008000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4 = 0x00070000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4 = 0x00080000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5 = 0x00700000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5 = 0x00800000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6 = 0x07000000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6 = 0x08000000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7 = 0x70000000U,
 
  INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7 = 0x80000000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0 = 0x00000007U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0 = 0x00000008U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1 = 0x00000070U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1 = 0x00000080U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2 = 0x00000700U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2 = 0x00000800U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3 = 0x00007000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3 = 0x00008000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4 = 0x00070000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4 = 0x00080000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5 = 0x00700000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5 = 0x00800000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6 = 0x07000000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6 = 0x08000000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7 = 0x70000000U,
 
  INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7 = 0x80000000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0 = 0x00000007U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0 = 0x00000008U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1 = 0x00000070U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1 = 0x00000080U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2 = 0x00000700U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2 = 0x00000800U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3 = 0x00007000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3 = 0x00008000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4 = 0x00070000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4 = 0x00080000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5 = 0x00700000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5 = 0x00800000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6 = 0x07000000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6 = 0x08000000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7 = 0x70000000U,
 
  INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7 = 0x80000000U
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_4B503756_C9BF_4641_86B8_961ABEA7AB89 */