syscon/Shift.h

 
#ifndef CHIP_B2B1FF5C_F0E6_463C_A8D4_CCC7B30DF57B
#define CHIP_B2B1FF5C_F0E6_463C_A8D4_CCC7B30DF57B
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::syscon {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::syscon
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::syscon::Shift : unsigned int {
  REMAP_CPU0_SBUS = 0U,
 
  REMAP_DMA0 = 2U,
 
  REMAP_USB0 = 4U,
 
  REMAP_LOCK = 31U,
 
  AHBMATPRIO_CPU0_CBUS = 0U,
 
  AHBMATPRIO_CPU0_SBUS = 2U,
 
  AHBMATPRIO_DMA0 = 8U,
 
  AHBMATPRIO_USB_FS_ENET = 24U,
 
  CPU0NSTCKCAL_TENMS = 0U,
 
  CPU0NSTCKCAL_SKEW = 24U,
 
  CPU0NSTCKCAL_NOREF = 25U,
 
  NMISRC_IRQCPU0 = 0U,
 
  NMISRC_NMIENCPU0 = 31U,
 
  SLOWCLKDIV_RESET = 29U,
 
  SLOWCLKDIV_HALT = 30U,
 
  SLOWCLKDIV_UNSTAB = 31U,
 
  AHBCLKDIV_DIV = 0U,
 
  AHBCLKDIV_UNSTAB = 31U,
 
  CLKUNLOCK_UNLOCK = 0U,
 
  NVM_CTRL_DIS_FLASH_SPEC = 0U,
 
  NVM_CTRL_DIS_DATA_SPEC = 1U,
 
  NVM_CTRL_FLASH_STALL_EN = 10U,
 
  NVM_CTRL_DIS_MBECC_ERR_INST = 16U,
 
  NVM_CTRL_DIS_MBECC_ERR_DATA = 17U,
 
  CPUSTAT_CPU0SLEEPING = 0U,
 
  CPUSTAT_CPU0LOCKUP = 2U,
 
  LPCAC_CTRL_DIS_LPCAC = 0U,
 
  LPCAC_CTRL_CLR_LPCAC = 1U,
 
  LPCAC_CTRL_FRC_NO_ALLOC = 2U,
 
  LPCAC_CTRL_DIS_LPCAC_WTBF = 4U,
 
  LPCAC_CTRL_LIM_LPCAC_WTBF = 5U,
 
  LPCAC_CTRL_LPCAC_XOM = 7U,
 
  LPCAC_CTRL_LPCAC_MEM_REQ = 8U,
 
  PWM0SUBCTL_CLK0_EN = 0U,
 
  PWM0SUBCTL_CLK1_EN = 1U,
 
  PWM0SUBCTL_CLK2_EN = 2U,
 
  PWM0SUBCTL_CLK3_EN = 3U,
 
  PWM1SUBCTL_CLK0_EN = 0U,
 
  PWM1SUBCTL_CLK1_EN = 1U,
 
  PWM1SUBCTL_CLK2_EN = 2U,
 
  PWM1SUBCTL_CLK3_EN = 3U,
 
  CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN = 0U,
 
  CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN = 1U,
 
  CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN = 2U,
 
  CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN = 3U,
 
  CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN = 4U,
 
  RAM_CTRL_RAMA_ECC_ENABLE = 0U,
 
  RAM_CTRL_RAMA_CG_OVERRIDE = 16U,
 
  RAM_CTRL_RAMX_CG_OVERRIDE = 17U,
 
  RAM_CTRL_RAMB_CG_OVERRIDE = 18U,
 
  GRAY_CODE_LSB_code_gray_31_0 = 0U,
 
  GRAY_CODE_MSB_code_gray_41_32 = 0U,
 
  BINARY_CODE_LSB_code_bin_31_0 = 0U,
 
  BINARY_CODE_MSB_code_bin_41_32 = 0U,
 
  ROP_STATE_ROP_STATE = 0U,
 
  OVP_PAD_STATE_OVP_PAD_STATE = 0U,
 
  PROBE_STATE_PROBE_STATE = 0U,
 
  FT_STATE_A_FT_STATE_A = 0U,
 
  FT_STATE_B_FT_STATE_B = 0U,
 
  SRAM_XEN_RAMX0_XEN = 0U,
 
  SRAM_XEN_RAMX1_XEN = 1U,
 
  SRAM_XEN_RAMA0_XEN = 2U,
 
  SRAM_XEN_RAMA1_XEN = 3U,
 
  SRAM_XEN_RAMB_XEN = 4U,
 
  SRAM_XEN_LOCK = 31U,
 
  SRAM_XEN_DP_RAMX0_XEN = 0U,
 
  SRAM_XEN_DP_RAMX1_XEN = 1U,
 
  SRAM_XEN_DP_RAMA0_XEN = 2U,
 
  SRAM_XEN_DP_RAMA1_XEN = 3U,
 
  SRAM_XEN_DP_RAMB_XEN = 4U,
 
  ELS_OTP_LC_STATE_OTP_LC_STATE = 0U,
 
  ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP = 0U,
 
  DEBUG_LOCK_EN_LOCK_ALL = 0U,
 
  DEBUG_FEATURES_CPU0_DBGEN = 0U,
 
  DEBUG_FEATURES_CPU0_NIDEN = 2U,
 
  DEBUG_FEATURES_DP_CPU0_DBGEN = 0U,
 
  DEBUG_FEATURES_DP_CPU0_NIDEN = 2U,
 
  SWD_ACCESS_CPU0_SEC_CODE = 0U,
 
  DEBUG_AUTH_BEACON_BEACON = 0U,
 
  JTAG_ID_JTAG_ID = 0U,
 
  DEVICE_TYPE_DEVICE_TYPE = 0U,
 
  DEVICE_ID0_RAM_SIZE = 0U,
 
  DEVICE_ID0_FLASH_SIZE = 4U,
 
  DEVICE_ID0_SECURITY = 24U,
 
  DIEID_MINOR_REVISION = 0U,
 
  DIEID_MAJOR_REVISION = 4U,
 
  DIEID_MCO_NUM_IN_DIE_ID = 8U
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_B2B1FF5C_F0E6_463C_A8D4_CCC7B30DF57B */