fmu/Shift.h

 
#ifndef CHIP_C838EA84_59FC_45BC_A702_2A064A0A1CE7
#define CHIP_C838EA84_59FC_45BC_A702_2A064A0A1CE7
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::fmu {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::fmu
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::fmu::Shift : unsigned int {
 
  FSTAT_FAIL = 0U,
 
  FSTAT_CMDABT = 2U,
 
  FSTAT_PVIOL = 4U,
 
  FSTAT_ACCERR = 5U,
 
  FSTAT_CWSABT = 6U,
 
  FSTAT_CCIF = 7U,
 
  FSTAT_CMDPRT = 8U,
 
  FSTAT_CMDP = 11U,
 
  FSTAT_CMDDID = 12U,
 
  FSTAT_DFDIF = 16U,
 
  FSTAT_SALV_USED = 17U,
 
  FSTAT_PEWEN = 24U,
 
  FSTAT_PERDY = 31U,
 
  FCNFG_CCIE = 7U,
 
  FCNFG_ERSREQ = 8U,
 
  FCNFG_DFDIE = 16U,
 
  FCNFG_ERSIEN0 = 24U,
 
  FCNFG_ERSIEN1 = 28U,
 
  FCTRL_RWSC = 0U,
 
  FCTRL_LSACTIVE = 8U,
 
  FCTRL_FDFD = 16U,
 
  FCTRL_ABTREQ = 24U,
 
  FTEST_TMECTL = 0U,
 
  FTEST_TMEWR = 1U,
 
  FTEST_TME = 2U,
 
  FTEST_TMODE = 3U,
 
  FTEST_TMELOCK = 4U,
 
  FCCOB0_CMDCODE = 0U,
 
  FCCOB1_CMDOPT = 0U,
 
  FCCOB2_CMDADDR = 0U,
 
  FCCOB3_CMDADDRE = 0U,
 
  FCCOB4_CMDDATA0 = 0U,
 
  FCCOB5_CMDDATA1 = 0U,
 
  FCCOB6_CMDDATA2 = 0U,
 
  FCCOB7_CMDDATA3 = 0U,
 
  RESET_STATUS_ARY_TRIM_DONE = 0U,
 
  RESET_STATUS_FMU_PARM_EN = 1U,
 
  RESET_STATUS_FMU_PARM_DONE = 2U,
 
  RESET_STATUS_SOC_TRIM_EN = 3U,
 
  RESET_STATUS_SOC_TRIM_ECC = 4U,
 
  RESET_STATUS_SOC_TRIM_DONE = 5U,
 
  RESET_STATUS_RPR_DONE = 6U,
 
  RESET_STATUS_INIT_DONE = 7U,
 
  RESET_STATUS_RST_SF_ERR = 8U,
 
  RESET_STATUS_RST_DF_ERR = 9U,
 
  RESET_STATUS_SOC_TRIM_DF_ERR = 10U,
 
  RESET_STATUS_RST_PATCH_LD = 18U,
 
  RESET_STATUS_RECALL_DATA_MISMATCH = 19U,
 
  MCTL_COREHLD = 0U,
 
  MCTL_LSACT_EN = 2U,
 
  MCTL_LSACTWREN = 3U,
 
  MCTL_MASTER_REPAIR_EN = 4U,
 
  MCTL_RFCMDEN = 5U,
 
  MCTL_CWSABTEN = 6U,
 
  MCTL_MRGRDDIS = 7U,
 
  MCTL_MRGRD0 = 8U,
 
  MCTL_MRGRD1 = 12U,
 
  MCTL_ERSAACK = 16U,
 
  MCTL_SCAN_OBS = 19U,
 
  MCTL_BIST_CTL = 20U,
 
  MCTL_SMWR_CTL = 21U,
 
  MCTL_SALV_DIS = 24U,
 
  MCTL_SOC_ECC_CTL = 25U,
 
  MCTL_FMU_ECC_CTL = 26U,
 
  MCTL_BIST_PWR_DIS = 29U,
 
  MCTL_OSC_H = 31U,
 
  BSEL_GEN_SBSEL_GEN = 0U,
 
  BSEL_GEN_MBSEL_GEN = 8U,
 
  PWR_OPT_PD_CDIV = 0U,
 
  PWR_OPT_SLM_COUNT = 16U,
 
  PWR_OPT_PD_TIMER_EN = 31U,
 
  CMD_CHECK_ALIGNFAIL_PHR = 0U,
 
  CMD_CHECK_ALIGNFAIL_PG = 1U,
 
  CMD_CHECK_ALIGNFAIL_SCR = 2U,
 
  CMD_CHECK_ALIGNFAIL_BLK = 3U,
 
  CMD_CHECK_ADDR_FAIL = 4U,
 
  CMD_CHECK_IFR_CMD = 5U,
 
  CMD_CHECK_ALL_CMD = 6U,
 
  CMD_CHECK_RANGE_FAIL = 7U,
 
  CMD_CHECK_SCR_ALIGN_CHK = 8U,
 
  CMD_CHECK_OPTION_FAIL = 9U,
 
  CMD_CHECK_ILLEGAL_CMD = 10U,
 
  BSEL_SBSEL = 0U,
 
  BSEL_MBSEL = 8U,
 
  MSIZE_MAXADDR0 = 0U,
 
  FLASH_RD_ADD_FLASH_RD_ADD = 0U,
 
  FLASH_STOP_ADD_FLASH_STOP_ADD = 0U,
 
  FLASH_RD_CTRL_FLASH_RD = 0U,
 
  FLASH_RD_CTRL_WIDE_LOAD = 1U,
 
  FLASH_RD_CTRL_SINGLE_RD = 2U,
 
  MM_ADDR_MM_ADDR = 0U,
 
  MM_WDATA_MM_WDATA = 0U,
 
  MM_CTL_MM_SEL = 0U,
 
  MM_CTL_MM_RD = 1U,
 
  MM_CTL_BIST_ON = 2U,
 
  MM_CTL_FORCE_SW_CLK = 3U,
 
  UINT_CTL_SET_FAIL = 0U,
 
  UINT_CTL_DBERR = 1U,
 
  RD_DATA0_RD_DATA0 = 0U,
 
  RD_DATA1_RD_DATA1 = 0U,
 
  RD_DATA2_RD_DATA2 = 0U,
 
  RD_DATA3_RD_DATA3 = 0U,
 
  PARITY_PARITY = 0U,
 
  RD_PATH_CTRL_STATUS_RD_CAPT = 0U,
 
  RD_PATH_CTRL_STATUS_SE_SIZE = 8U,
 
  RD_PATH_CTRL_STATUS_ECC_ENABLEB = 16U,
 
  RD_PATH_CTRL_STATUS_MISR_EN = 17U,
 
  RD_PATH_CTRL_STATUS_CPY_PAR_EN = 18U,
 
  RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW = 19U,
 
  RD_PATH_CTRL_STATUS_AD_SET = 20U,
 
  RD_PATH_CTRL_STATUS_WR_PATH_EN = 24U,
 
  RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN = 25U,
 
  RD_PATH_CTRL_STATUS_DBERR_REG = 26U,
 
  RD_PATH_CTRL_STATUS_SBERR_REG = 27U,
 
  RD_PATH_CTRL_STATUS_CPY_PHRASE_EN = 28U,
 
  RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL = 29U,
 
  RD_PATH_CTRL_STATUS_BIST_ECC_EN = 30U,
 
  RD_PATH_CTRL_STATUS_LAST_READ = 31U,
 
  SMW_DIN0_SMW_DIN0 = 0U,
 
  SMW_DIN1_SMW_DIN1 = 0U,
 
  SMW_DIN2_SMW_DIN2 = 0U,
 
  SMW_DIN3_SMW_DIN3 = 0U,
 
  SMW_ADDR_SMW_ADDR = 0U,
 
  SMW_CMD_WAIT_CMD = 0U,
 
  SMW_CMD_WAIT_WAIT_EN = 3U,
 
  SMW_CMD_WAIT_WAIT_AUTO_SET = 4U,
 
  SMW_STATUS_SMW_ERR = 0U,
 
  SMW_STATUS_SMW_BUSY = 1U,
 
  SMW_STATUS_BIST_BUSY = 2U,
 
  SOCTRIM0_0_TRIM0_0 = 0U,
 
  SOCTRIM0_1_TRIM0_1 = 0U,
 
  SOCTRIM0_2_TRIM0_2 = 0U,
 
  SOCTRIM0_3_TRIM0_3 = 0U,
 
  SOCTRIM1_0_TRIM1_0 = 0U,
 
  SOCTRIM1_1_TRIM1_1 = 0U,
 
  SOCTRIM1_2_TRIM1_2 = 0U,
 
  SOCTRIM1_3_TRIM1_3 = 0U,
 
  SOCTRIM2_0_TRIM2_0 = 0U,
 
  SOCTRIM2_1_TRIM2_1 = 0U,
 
  SOCTRIM2_2_TRIM2_2 = 0U,
 
  SOCTRIM2_3_TRIM2_3 = 0U,
 
  SOCTRIM3_0_TRIM3_0 = 0U,
 
  SOCTRIM3_1_TRIM3_1 = 0U,
 
  SOCTRIM3_2_TRIM3_2 = 0U,
 
  SOCTRIM3_3_TRIM3_3 = 0U,
 
  SOCTRIM4_0_TRIM4_0 = 0U,
 
  SOCTRIM4_1_TRIM4_1 = 0U,
 
  SOCTRIM4_2_TRIM4_2 = 0U,
 
  SOCTRIM4_3_TRIM4_3 = 0U,
 
  SOCTRIM5_0_TRIM5_0 = 0U,
 
  SOCTRIM5_1_TRIM5_1 = 0U,
 
  SOCTRIM5_2_TRIM5_2 = 0U,
 
  SOCTRIM5_3_TRIM5_3 = 0U,
 
  SOCTRIM6_0_TRIM6_0 = 0U,
 
  SOCTRIM6_1_TRIM6_1 = 0U,
 
  SOCTRIM6_2_TRIM6_2 = 0U,
 
  SOCTRIM6_3_TRIM6_3 = 0U,
 
  SOCTRIM7_0_TRIM7_0 = 0U,
 
  SOCTRIM7_1_TRIM7_1 = 0U,
 
  SOCTRIM7_2_TRIM7_2 = 0U,
 
  SOCTRIM7_3_TRIM7_3 = 0U,
 
  R_IP_CONFIG_IPSEL0 = 0U,
 
  R_IP_CONFIG_IPSEL1 = 2U,
 
  R_IP_CONFIG_BIST_CDIVL = 4U,
 
  R_IP_CONFIG_CDIVS = 12U,
 
  R_IP_CONFIG_BIST_TVFY = 15U,
 
  R_IP_CONFIG_TSTCTL = 20U,
 
  R_IP_CONFIG_DBGCTL = 22U,
 
  R_IP_CONFIG_BIST_CLK_SEL = 23U,
 
  R_IP_CONFIG_SMWTST = 24U,
 
  R_IP_CONFIG_ECCEN = 26U,
 
  R_TESTCODE_TESTCODE = 0U,
 
  R_DFT_CTRL_DFT_XADR = 0U,
 
  R_DFT_CTRL_DFT_YADR = 4U,
 
  R_DFT_CTRL_DFT_DATA = 8U,
 
  R_DFT_CTRL_CMP_MASK = 12U,
 
  R_DFT_CTRL_DFT_DATA_SRC = 14U,
 
  R_ADR_CTRL_GRPSEL = 0U,
 
  R_ADR_CTRL_XADR = 4U,
 
  R_ADR_CTRL_YADR = 16U,
 
  R_ADR_CTRL_PROG_ATTR = 21U,
 
  R_DATA_CTRL0_DATA0 = 0U,
 
  R_PIN_CTRL_MAS1 = 0U,
 
  R_PIN_CTRL_IFREN = 1U,
 
  R_PIN_CTRL_IFREN1 = 2U,
 
  R_PIN_CTRL_REDEN = 3U,
 
  R_PIN_CTRL_LVE = 4U,
 
  R_PIN_CTRL_PV = 5U,
 
  R_PIN_CTRL_EV = 6U,
 
  R_PIN_CTRL_WIPGM = 7U,
 
  R_PIN_CTRL_WHV = 9U,
 
  R_PIN_CTRL_WMV = 13U,
 
  R_PIN_CTRL_XE = 16U,
 
  R_PIN_CTRL_YE = 17U,
 
  R_PIN_CTRL_SE = 18U,
 
  R_PIN_CTRL_ERASE = 19U,
 
  R_PIN_CTRL_PROG = 20U,
 
  R_PIN_CTRL_NVSTR = 21U,
 
  R_PIN_CTRL_SLM = 22U,
 
  R_PIN_CTRL_RECALL = 23U,
 
  R_PIN_CTRL_HEM = 24U,
 
  R_CNT_LOOP_CTRL_LOOPCNT = 0U,
 
  R_CNT_LOOP_CTRL_LOOPOPT = 12U,
 
  R_CNT_LOOP_CTRL_LOOPUNIT = 15U,
 
  R_CNT_LOOP_CTRL_LOOPDLY = 18U,
 
  R_TIMER_CTRL_TNVSUNIT = 0U,
 
  R_TIMER_CTRL_TNVSDLY = 3U,
 
  R_TIMER_CTRL_TNVHUNIT = 7U,
 
  R_TIMER_CTRL_TNVHDLY = 10U,
 
  R_TIMER_CTRL_TPGSUNIT = 14U,
 
  R_TIMER_CTRL_TPGSDLY = 17U,
 
  R_TIMER_CTRL_TRCVUNIT = 21U,
 
  R_TIMER_CTRL_TRCVDLY = 24U,
 
  R_TIMER_CTRL_TLVSUNIT = 28U,
 
  R_TIMER_CTRL_TLVSDLY_L = 31U,
 
  R_TEST_CTRL_BUSY = 0U,
 
  R_TEST_CTRL_DEBUG = 1U,
 
  R_TEST_CTRL_STATUS0 = 2U,
 
  R_TEST_CTRL_STATUS1 = 3U,
 
  R_TEST_CTRL_DEBUGRUN = 4U,
 
  R_TEST_CTRL_STARTRUN = 5U,
 
  R_TEST_CTRL_CMDINDEX = 6U,
 
  R_TEST_CTRL_DISABLE_IP1 = 16U,
 
  R_ABORT_LOOP_ABORT_LOOP = 0U,
 
  R_ADR_QUERY_YADRFAIL = 0U,
 
  R_ADR_QUERY_XADRFAIL = 5U,
 
  R_DOUT_QUERY0_DOUTFAIL = 0U,
 
  R_SMW_QUERY_SMWLOOP = 0U,
 
  R_SMW_QUERY_SMWLAST = 10U,
 
  R_SMW_SETTING0_SMWPARM0 = 0U,
 
  R_SMW_SETTING1_SMWPARM1 = 0U,
 
  R_SMP_WHV0_SMPWHV0 = 0U,
 
  R_SMP_WHV1_SMPWHV1 = 0U,
 
  R_SME_WHV0_SMEWHV0 = 0U,
 
  R_SME_WHV1_SMEWHV1 = 0U,
 
  R_SMW_SETTING2_SMWPARM2 = 0U,
 
  R_D_MISR0_DATASIG0 = 0U,
 
  R_A_MISR0_ADRSIG0 = 0U,
 
  R_C_MISR0_CTRLSIG0 = 0U,
 
  R_SMW_SETTING3_SMWPARM3 = 0U,
 
  R_DATA_CTRL1_DATA1 = 0U,
 
  R_DATA_CTRL2_DATA2 = 0U,
 
  R_DATA_CTRL3_DATA3 = 0U,
 
  R_REPAIR0_0_RDIS0_0 = 0U,
 
  R_REPAIR0_0_RADR0_0 = 1U,
 
  R_REPAIR0_1_RDIS0_1 = 0U,
 
  R_REPAIR0_1_RADR0_1 = 1U,
 
  R_REPAIR1_0_RDIS1_0 = 0U,
 
  R_REPAIR1_0_RADR1_0 = 1U,
 
  R_REPAIR1_1_RDIS1_1 = 0U,
 
  R_REPAIR1_1_RADR1_1 = 1U,
 
  R_DATA_CTRL0_EX_DATA0X = 0U,
 
  R_TIMER_CTRL_EX_TLVSDLY_H = 0U,
 
  R_DOUT_QUERY1_DOUT = 0U,
 
  R_D_MISR1_DATASIG1 = 0U,
 
  R_A_MISR1_ADRSIG1 = 0U,
 
  R_C_MISR1_CTRLSIG1 = 0U,
 
  R_DATA_CTRL1_EX_DATA1X = 0U,
 
  R_DATA_CTRL2_EX_DATA2X = 0U,
 
  R_DATA_CTRL3_EX_DATA3X = 0U,
 
  SMW_TIMER_OPTION_SMW_CDIVL = 0U,
 
  SMW_TIMER_OPTION_SMW_TVFY = 8U,
 
  SMW_SETTING_OPTION0_MV_INIT = 14U,
 
  SMW_SETTING_OPTION0_MV_END = 17U,
 
  SMW_SETTING_OPTION0_MV_MISC = 20U,
 
  SMW_SETTING_OPTION0_IPGM_INIT = 24U,
 
  SMW_SETTING_OPTION0_IPGM_END = 26U,
 
  SMW_SETTING_OPTION0_IPGM_MISC = 28U,
 
  SMW_SETTING_OPTION2_THVS_CTRL = 0U,
 
  SMW_SETTING_OPTION2_TRCV_CTRL = 3U,
 
  SMW_SETTING_OPTION2_XTRA_ERS = 6U,
 
  SMW_SETTING_OPTION2_XTRA_PGM = 8U,
 
  SMW_SETTING_OPTION2_WHV_CNTR = 10U,
 
  SMW_SETTING_OPTION2_POST_TERS = 18U,
 
  SMW_SETTING_OPTION2_POST_TPGM = 21U,
 
  SMW_SETTING_OPTION2_VFY_OPT = 23U,
 
  SMW_SETTING_OPTION2_TPGM_OPT = 25U,
 
  SMW_SETTING_OPTION2_MASK0_OPT = 27U,
 
  SMW_SETTING_OPTION2_DIS_PRER = 28U,
 
  SMW_SETTING_OPTION3_HEM_WHV_CNTR = 0U,
 
  SMW_SETTING_OPTION3_HEM_MAX_ERS = 8U,
 
  SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0 = 0U,
 
  SMW_SME_WHV_OPTION0_SME_WHV_OPT0 = 0U,
 
  SMW_SETTING_OPTION1_TERS_CTRL0 = 0U,
 
  SMW_SETTING_OPTION1_TPGM_CTRL = 3U,
 
  SMW_SETTING_OPTION1_TNVS_CTRL = 5U,
 
  SMW_SETTING_OPTION1_TNVH_CTRL = 8U,
 
  SMW_SETTING_OPTION1_TPGS_CTRL = 11U,
 
  SMW_SETTING_OPTION1_MAX_ERASE = 14U,
 
  SMW_SETTING_OPTION1_MAX_PROG = 23U,
 
  SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1 = 0U,
 
  SMW_SME_WHV_OPTION1_SME_WHV_OPT1 = 0U,
 
  REPAIR0_0_RDIS0_0 = 0U,
 
  REPAIR0_0_RADR0_0 = 1U,
 
  REPAIR0_1_RDIS0_1 = 0U,
 
  REPAIR0_1_RADR0_1 = 1U,
 
  REPAIR1_0_RDIS1_0 = 0U,
 
  REPAIR1_0_RADR1_0 = 1U,
 
  REPAIR1_1_RDIS1_1 = 0U,
 
  REPAIR1_1_RADR1_1 = 1U,
 
  SMW_HB_SIGNALS_SMW_ARRAY = 0U,
 
  SMW_HB_SIGNALS_USER_IFREN1 = 3U,
 
  SMW_HB_SIGNALS_USER_PV = 4U,
 
  SMW_HB_SIGNALS_USER_EV = 5U,
 
  SMW_HB_SIGNALS_USER_IFREN = 6U,
 
  SMW_HB_SIGNALS_USER_REDEN = 7U,
 
  SMW_HB_SIGNALS_USER_HEM = 8U,
 
  BIST_DUMP_CTRL_BIST_DONE = 16U,
 
  BIST_DUMP_CTRL_BIST_FAIL = 17U,
 
  BIST_DUMP_CTRL_DATADUMP = 18U,
 
  BIST_DUMP_CTRL_DATADUMP_TRIG = 19U,
 
  BIST_DUMP_CTRL_DATADUMP_PATT = 20U,
 
  BIST_DUMP_CTRL_DATADUMP_MRGEN = 22U,
 
  BIST_DUMP_CTRL_DATADUMP_MRGTYPE = 23U,
 
  ATX_PIN_CTRL_TM_TO_ATX = 0U,
 
  FAILCNT_FAILCNT = 0U,
 
  PGM_PULSE_CNT0_PGM_CNT0 = 0U,
 
  PGM_PULSE_CNT1_PGM_CNT1 = 0U,
 
  ERS_PULSE_CNT_ERS_CNT0 = 0U,
 
  ERS_PULSE_CNT_ERS_CNT1 = 16U,
 
  MAX_PULSE_CNT_LAST_PCNT = 0U,
 
  MAX_PULSE_CNT_MAX_ERS_CNT = 16U,
 
  MAX_PULSE_CNT_MAX_PGM_CNT = 27U,
 
  PORT_CTRL_BDONE_SEL = 0U,
 
  PORT_CTRL_BSDO_SEL = 2U
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_C838EA84_59FC_45BC_A702_2A064A0A1CE7 */