fmu/Mask.h

 
#ifndef CHIP_2939105B_92A4_4B9F_8147_0850454FD025
#define CHIP_2939105B_92A4_4B9F_8147_0850454FD025
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::fmu {
  enum struct Mask : unsigned int;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::fmu
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct chip::fmu::Mask : unsigned int {
 
  FSTAT_FAIL = 0x1U,
 
  FSTAT_CMDABT = 0x4U,
 
  FSTAT_PVIOL = 0x10U,
 
  FSTAT_ACCERR = 0x20U,
 
  FSTAT_CWSABT = 0x40U,
 
  FSTAT_CCIF = 0x80U,
 
  FSTAT_CMDPRT = 0x300U,
 
  FSTAT_CMDP = 0x800U,
 
  FSTAT_CMDDID = 0xF000U,
 
  FSTAT_DFDIF = 0x10000U,
 
  FSTAT_SALV_USED = 0x20000U,
 
  FSTAT_PEWEN = 0x3000000U,
 
  FSTAT_PERDY = 0x80000000U,
 
  FCNFG_CCIE = 0x80U,
 
  FCNFG_ERSREQ = 0x100U,
 
  FCNFG_DFDIE = 0x10000U,
 
  FCNFG_ERSIEN0 = 0xF000000U,
 
  FCNFG_ERSIEN1 = 0xF0000000U,
 
  FCTRL_RWSC = 0xFU,
 
  FCTRL_LSACTIVE = 0x100U,
 
  FCTRL_FDFD = 0x10000U,
 
  FCTRL_ABTREQ = 0x1000000U,
 
  FTEST_TMECTL = 0x1U,
 
  FTEST_TMEWR = 0x2U,
 
  FTEST_TME = 0x4U,
 
  FTEST_TMODE = 0x8U,
 
  FTEST_TMELOCK = 0x10U,
 
  FCCOB0_CMDCODE = 0xFFU,
 
  FCCOB1_CMDOPT = 0xFFU,
 
  FCCOB2_CMDADDR = 0xFFFFFFFFU,
 
  FCCOB3_CMDADDRE = 0xFFFFFFFFU,
 
  FCCOB4_CMDDATA0 = 0xFFFFFFFFU,
 
  FCCOB5_CMDDATA1 = 0xFFFFFFFFU,
 
  FCCOB6_CMDDATA2 = 0xFFFFFFFFU,
 
  FCCOB7_CMDDATA3 = 0xFFFFFFFFU,
 
  RESET_STATUS_ARY_TRIM_DONE = 0x1U,
 
  RESET_STATUS_FMU_PARM_EN = 0x2U,
 
  RESET_STATUS_FMU_PARM_DONE = 0x4U,
 
  RESET_STATUS_SOC_TRIM_EN = 0x8U,
 
  RESET_STATUS_SOC_TRIM_ECC = 0x10U,
 
  RESET_STATUS_SOC_TRIM_DONE = 0x20U,
 
  RESET_STATUS_RPR_DONE = 0x40U,
 
  RESET_STATUS_INIT_DONE = 0x80U,
 
  RESET_STATUS_RST_SF_ERR = 0x100U,
 
  RESET_STATUS_RST_DF_ERR = 0x200U,
 
  RESET_STATUS_SOC_TRIM_DF_ERR = 0x3FC00U,
 
  RESET_STATUS_RST_PATCH_LD = 0x40000U,
 
  RESET_STATUS_RECALL_DATA_MISMATCH = 0x80000U,
 
  MCTL_COREHLD = 0x1U,
 
  MCTL_LSACT_EN = 0x4U,
 
  MCTL_LSACTWREN = 0x8U,
 
  MCTL_MASTER_REPAIR_EN = 0x10U,
 
  MCTL_RFCMDEN = 0x20U,
 
  MCTL_CWSABTEN = 0x40U,
 
  MCTL_MRGRDDIS = 0x80U,
 
  MCTL_MRGRD0 = 0xF00U,
 
  MCTL_MRGRD1 = 0xF000U,
 
  MCTL_ERSAACK = 0x10000U,
 
  MCTL_SCAN_OBS = 0x80000U,
 
  MCTL_BIST_CTL = 0x100000U,
 
  MCTL_SMWR_CTL = 0x200000U,
 
  MCTL_SALV_DIS = 0x1000000U,
 
  MCTL_SOC_ECC_CTL = 0x2000000U,
 
  MCTL_FMU_ECC_CTL = 0x4000000U,
 
  MCTL_BIST_PWR_DIS = 0x20000000U,
 
  MCTL_OSC_H = 0x80000000U,
 
  BSEL_GEN_SBSEL_GEN = 0x3U,
 
  BSEL_GEN_MBSEL_GEN = 0x300U,
 
  PWR_OPT_PD_CDIV = 0xFFU,
 
  PWR_OPT_SLM_COUNT = 0x3FF0000U,
 
  PWR_OPT_PD_TIMER_EN = 0x80000000U,
 
  CMD_CHECK_ALIGNFAIL_PHR = 0x1U,
 
  CMD_CHECK_ALIGNFAIL_PG = 0x2U,
 
  CMD_CHECK_ALIGNFAIL_SCR = 0x4U,
 
  CMD_CHECK_ALIGNFAIL_BLK = 0x8U,
 
  CMD_CHECK_ADDR_FAIL = 0x10U,
 
  CMD_CHECK_IFR_CMD = 0x20U,
 
  CMD_CHECK_ALL_CMD = 0x40U,
 
  CMD_CHECK_RANGE_FAIL = 0x80U,
 
  CMD_CHECK_SCR_ALIGN_CHK = 0x100U,
 
  CMD_CHECK_OPTION_FAIL = 0x200U,
 
  CMD_CHECK_ILLEGAL_CMD = 0x400U,
 
  BSEL_SBSEL = 0x3U,
 
  BSEL_MBSEL = 0x300U,
 
  MSIZE_MAXADDR0 = 0xFFU,
 
  FLASH_RD_ADD_FLASH_RD_ADD = 0xFFFFFFFFU,
 
  FLASH_STOP_ADD_FLASH_STOP_ADD = 0xFFFFFFFFU,
 
  FLASH_RD_CTRL_FLASH_RD = 0x1U,
 
  FLASH_RD_CTRL_WIDE_LOAD = 0x2U,
 
  FLASH_RD_CTRL_SINGLE_RD = 0x4U,
 
  MM_ADDR_MM_ADDR = 0xFFFFFFFFU,
 
  MM_WDATA_MM_WDATA = 0xFFFFFFFFU,
 
  MM_CTL_MM_SEL = 0x1U,
 
  MM_CTL_MM_RD = 0x2U,
 
  MM_CTL_BIST_ON = 0x4U,
 
  MM_CTL_FORCE_SW_CLK = 0x8U,
 
  UINT_CTL_SET_FAIL = 0x1U,
 
  UINT_CTL_DBERR = 0x2U,
 
  RD_DATA0_RD_DATA0 = 0xFFFFFFFFU,
 
  RD_DATA1_RD_DATA1 = 0xFFFFFFFFU,
 
  RD_DATA2_RD_DATA2 = 0xFFFFFFFFU,
 
  RD_DATA3_RD_DATA3 = 0xFFFFFFFFU,
 
  PARITY_PARITY = 0x1FFU,
 
  RD_PATH_CTRL_STATUS_RD_CAPT = 0xFFU,
 
  RD_PATH_CTRL_STATUS_SE_SIZE = 0xFF00U,
 
  RD_PATH_CTRL_STATUS_ECC_ENABLEB = 0x10000U,
 
  RD_PATH_CTRL_STATUS_MISR_EN = 0x20000U,
 
  RD_PATH_CTRL_STATUS_CPY_PAR_EN = 0x40000U,
 
  RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW = 0x80000U,
 
  RD_PATH_CTRL_STATUS_AD_SET = 0xF00000U,
 
  RD_PATH_CTRL_STATUS_WR_PATH_EN = 0x1000000U,
 
  RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN = 0x2000000U,
 
  RD_PATH_CTRL_STATUS_DBERR_REG = 0x4000000U,
 
  RD_PATH_CTRL_STATUS_SBERR_REG = 0x8000000U,
 
  RD_PATH_CTRL_STATUS_CPY_PHRASE_EN = 0x10000000U,
 
  RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL = 0x20000000U,
 
  RD_PATH_CTRL_STATUS_BIST_ECC_EN = 0x40000000U,
 
  RD_PATH_CTRL_STATUS_LAST_READ = 0x80000000U,
 
  SMW_DIN0_SMW_DIN0 = 0xFFFFFFFFU,
 
  SMW_DIN1_SMW_DIN1 = 0xFFFFFFFFU,
 
  SMW_DIN2_SMW_DIN2 = 0xFFFFFFFFU,
 
  SMW_DIN3_SMW_DIN3 = 0xFFFFFFFFU,
 
  SMW_ADDR_SMW_ADDR = 0xFFFFFFFFU,
 
  SMW_CMD_WAIT_CMD = 0x7U,
 
  SMW_CMD_WAIT_WAIT_EN = 0x8U,
 
  SMW_CMD_WAIT_WAIT_AUTO_SET = 0x10U,
 
  SMW_STATUS_SMW_ERR = 0x1U,
 
  SMW_STATUS_SMW_BUSY = 0x2U,
 
  SMW_STATUS_BIST_BUSY = 0x4U,
 
  SOCTRIM0_0_TRIM0_0 = 0xFFFFFFFFU,
 
  SOCTRIM0_1_TRIM0_1 = 0xFFFFFFFFU,
 
  SOCTRIM0_2_TRIM0_2 = 0xFFFFFFFFU,
 
  SOCTRIM0_3_TRIM0_3 = 0xFFFFFFFFU,
 
  SOCTRIM1_0_TRIM1_0 = 0xFFFFFFFFU,
 
  SOCTRIM1_1_TRIM1_1 = 0xFFFFFFFFU,
 
  SOCTRIM1_2_TRIM1_2 = 0xFFFFFFFFU,
 
  SOCTRIM1_3_TRIM1_3 = 0xFFFFFFFFU,
 
  SOCTRIM2_0_TRIM2_0 = 0xFFFFFFFFU,
 
  SOCTRIM2_1_TRIM2_1 = 0xFFFFFFFFU,
 
  SOCTRIM2_2_TRIM2_2 = 0xFFFFFFFFU,
 
  SOCTRIM2_3_TRIM2_3 = 0xFFFFFFFFU,
 
  SOCTRIM3_0_TRIM3_0 = 0xFFFFFFFFU,
 
  SOCTRIM3_1_TRIM3_1 = 0xFFFFFFFFU,
 
  SOCTRIM3_2_TRIM3_2 = 0xFFFFFFFFU,
 
  SOCTRIM3_3_TRIM3_3 = 0xFFFFFFFFU,
 
  SOCTRIM4_0_TRIM4_0 = 0xFFFFFFFFU,
 
  SOCTRIM4_1_TRIM4_1 = 0xFFFFFFFFU,
 
  SOCTRIM4_2_TRIM4_2 = 0xFFFFFFFFU,
 
  SOCTRIM4_3_TRIM4_3 = 0xFFFFFFFFU,
 
  SOCTRIM5_0_TRIM5_0 = 0xFFFFFFFFU,
 
  SOCTRIM5_1_TRIM5_1 = 0xFFFFFFFFU,
 
  SOCTRIM5_2_TRIM5_2 = 0xFFFFFFFFU,
 
  SOCTRIM5_3_TRIM5_3 = 0xFFFFFFFFU,
 
  SOCTRIM6_0_TRIM6_0 = 0xFFFFFFFFU,
 
  SOCTRIM6_1_TRIM6_1 = 0xFFFFFFFFU,
 
  SOCTRIM6_2_TRIM6_2 = 0xFFFFFFFFU,
 
  SOCTRIM6_3_TRIM6_3 = 0xFFFFFFFFU,
 
  SOCTRIM7_0_TRIM7_0 = 0xFFFFFFFFU,
 
  SOCTRIM7_1_TRIM7_1 = 0xFFFFFFFFU,
 
  SOCTRIM7_2_TRIM7_2 = 0xFFFFFFFFU,
 
  SOCTRIM7_3_TRIM7_3 = 0xFFFFFFFFU,
 
  R_IP_CONFIG_IPSEL0 = 0x3U,
 
  R_IP_CONFIG_IPSEL1 = 0xCU,
 
  R_IP_CONFIG_BIST_CDIVL = 0xFF0U,
 
  R_IP_CONFIG_CDIVS = 0x7000U,
 
  R_IP_CONFIG_BIST_TVFY = 0xF8000U,
 
  R_IP_CONFIG_TSTCTL = 0x300000U,
 
  R_IP_CONFIG_DBGCTL = 0x400000U,
 
  R_IP_CONFIG_BIST_CLK_SEL = 0x800000U,
 
  R_IP_CONFIG_SMWTST = 0x3000000U,
 
  R_IP_CONFIG_ECCEN = 0x4000000U,
 
  R_TESTCODE_TESTCODE = 0x3FU,
 
  R_DFT_CTRL_DFT_XADR = 0xFU,
 
  R_DFT_CTRL_DFT_YADR = 0xF0U,
 
  R_DFT_CTRL_DFT_DATA = 0xF00U,
 
  R_DFT_CTRL_CMP_MASK = 0x3000U,
 
  R_DFT_CTRL_DFT_DATA_SRC = 0x4000U,
 
  R_ADR_CTRL_GRPSEL = 0xFU,
 
  R_ADR_CTRL_XADR = 0xFFF0U,
 
  R_ADR_CTRL_YADR = 0x1F0000U,
 
  R_ADR_CTRL_PROG_ATTR = 0xE00000U,
 
  R_DATA_CTRL0_DATA0 = 0xFFFFFFFFU,
 
  R_PIN_CTRL_MAS1 = 0x1U,
 
  R_PIN_CTRL_IFREN = 0x2U,
 
  R_PIN_CTRL_IFREN1 = 0x4U,
 
  R_PIN_CTRL_REDEN = 0x8U,
 
  R_PIN_CTRL_LVE = 0x10U,
 
  R_PIN_CTRL_PV = 0x20U,
 
  R_PIN_CTRL_EV = 0x40U,
 
  R_PIN_CTRL_WIPGM = 0x180U,
 
  R_PIN_CTRL_WHV = 0x1E00U,
 
  R_PIN_CTRL_WMV = 0xE000U,
 
  R_PIN_CTRL_XE = 0x10000U,
 
  R_PIN_CTRL_YE = 0x20000U,
 
  R_PIN_CTRL_SE = 0x40000U,
 
  R_PIN_CTRL_ERASE = 0x80000U,
 
  R_PIN_CTRL_PROG = 0x100000U,
 
  R_PIN_CTRL_NVSTR = 0x200000U,
 
  R_PIN_CTRL_SLM = 0x400000U,
 
  R_PIN_CTRL_RECALL = 0x800000U,
 
  R_PIN_CTRL_HEM = 0x1000000U,
 
  R_CNT_LOOP_CTRL_LOOPCNT = 0xFFFU,
 
  R_CNT_LOOP_CTRL_LOOPOPT = 0x7000U,
 
  R_CNT_LOOP_CTRL_LOOPUNIT = 0x38000U,
 
  R_CNT_LOOP_CTRL_LOOPDLY = 0x1FC0000U,
 
  R_TIMER_CTRL_TNVSUNIT = 0x7U,
 
  R_TIMER_CTRL_TNVSDLY = 0x78U,
 
  R_TIMER_CTRL_TNVHUNIT = 0x380U,
 
  R_TIMER_CTRL_TNVHDLY = 0x3C00U,
 
  R_TIMER_CTRL_TPGSUNIT = 0x1C000U,
 
  R_TIMER_CTRL_TPGSDLY = 0x1E0000U,
 
  R_TIMER_CTRL_TRCVUNIT = 0xE00000U,
 
  R_TIMER_CTRL_TRCVDLY = 0xF000000U,
 
  R_TIMER_CTRL_TLVSUNIT = 0x70000000U,
 
  R_TIMER_CTRL_TLVSDLY_L = 0x80000000U,
 
  R_TEST_CTRL_BUSY = 0x1U,
 
  R_TEST_CTRL_DEBUG = 0x2U,
 
  R_TEST_CTRL_STATUS0 = 0x4U,
 
  R_TEST_CTRL_STATUS1 = 0x8U,
 
  R_TEST_CTRL_DEBUGRUN = 0x10U,
 
  R_TEST_CTRL_STARTRUN = 0x20U,
 
  R_TEST_CTRL_CMDINDEX = 0xFFC0U,
 
  R_TEST_CTRL_DISABLE_IP1 = 0x10000U,
 
  R_ABORT_LOOP_ABORT_LOOP = 0x1U,
 
  R_ADR_QUERY_YADRFAIL = 0x1FU,
 
  R_ADR_QUERY_XADRFAIL = 0x1FFE0U,
 
  R_DOUT_QUERY0_DOUTFAIL = 0xFFFFFFFFU,
 
  R_SMW_QUERY_SMWLOOP = 0x3FFU,
 
  R_SMW_QUERY_SMWLAST = 0x7FC00U,
 
  R_SMW_SETTING0_SMWPARM0 = 0x7FFFFFFFU,
 
  R_SMW_SETTING1_SMWPARM1 = 0xFFFFFFFU,
 
  R_SMP_WHV0_SMPWHV0 = 0xFFFFFFFFU,
 
  R_SMP_WHV1_SMPWHV1 = 0xFFFFFFFFU,
 
  R_SME_WHV0_SMEWHV0 = 0xFFFFFFFFU,
 
  R_SME_WHV1_SMEWHV1 = 0xFFFFFFFFU,
 
  R_SMW_SETTING2_SMWPARM2 = 0x1FFFFFFFU,
 
  R_D_MISR0_DATASIG0 = 0xFFFFFFFFU,
 
  R_A_MISR0_ADRSIG0 = 0xFFFFFFFFU,
 
  R_C_MISR0_CTRLSIG0 = 0xFFFFFFFFU,
 
  R_SMW_SETTING3_SMWPARM3 = 0x1FFFFU,
 
  R_DATA_CTRL1_DATA1 = 0xFFFFFFFFU,
 
  R_DATA_CTRL2_DATA2 = 0xFFFFFFFFU,
 
  R_DATA_CTRL3_DATA3 = 0xFFFFFFFFU,
 
  R_REPAIR0_0_RDIS0_0 = 0x1U,
 
  R_REPAIR0_0_RADR0_0 = 0x1FEU,
 
  R_REPAIR0_1_RDIS0_1 = 0x1U,
 
  R_REPAIR0_1_RADR0_1 = 0x1FEU,
 
  R_REPAIR1_0_RDIS1_0 = 0x1U,
 
  R_REPAIR1_0_RADR1_0 = 0x1FEU,
 
  R_REPAIR1_1_RDIS1_1 = 0x1U,
 
  R_REPAIR1_1_RADR1_1 = 0x1FEU,
 
  R_DATA_CTRL0_EX_DATA0X = 0x7U,
 
  R_TIMER_CTRL_EX_TLVSDLY_H = 0x7U,
 
  R_DOUT_QUERY1_DOUT = 0x7U,
 
  R_D_MISR1_DATASIG1 = 0xFFU,
 
  R_A_MISR1_ADRSIG1 = 0xFFU,
 
  R_C_MISR1_CTRLSIG1 = 0xFFU,
 
  R_DATA_CTRL1_EX_DATA1X = 0x7U,
 
  R_DATA_CTRL2_EX_DATA2X = 0x7U,
 
  R_DATA_CTRL3_EX_DATA3X = 0x7U,
 
  SMW_TIMER_OPTION_SMW_CDIVL = 0xFFU,
 
  SMW_TIMER_OPTION_SMW_TVFY = 0x1F00U,
 
  SMW_SETTING_OPTION0_MV_INIT = 0x1C000U,
 
  SMW_SETTING_OPTION0_MV_END = 0xE0000U,
 
  SMW_SETTING_OPTION0_MV_MISC = 0xF00000U,
 
  SMW_SETTING_OPTION0_IPGM_INIT = 0x3000000U,
 
  SMW_SETTING_OPTION0_IPGM_END = 0xC000000U,
 
  SMW_SETTING_OPTION0_IPGM_MISC = 0x70000000U,
 
  SMW_SETTING_OPTION2_THVS_CTRL = 0x7U,
 
  SMW_SETTING_OPTION2_TRCV_CTRL = 0x38U,
 
  SMW_SETTING_OPTION2_XTRA_ERS = 0xC0U,
 
  SMW_SETTING_OPTION2_XTRA_PGM = 0x300U,
 
  SMW_SETTING_OPTION2_WHV_CNTR = 0x3FC00U,
 
  SMW_SETTING_OPTION2_POST_TERS = 0x1C0000U,
 
  SMW_SETTING_OPTION2_POST_TPGM = 0x600000U,
 
  SMW_SETTING_OPTION2_VFY_OPT = 0x1800000U,
 
  SMW_SETTING_OPTION2_TPGM_OPT = 0x6000000U,
 
  SMW_SETTING_OPTION2_MASK0_OPT = 0x8000000U,
 
  SMW_SETTING_OPTION2_DIS_PRER = 0x10000000U,
 
  SMW_SETTING_OPTION3_HEM_WHV_CNTR = 0xFFU,
 
  SMW_SETTING_OPTION3_HEM_MAX_ERS = 0x1FF00U,
 
  SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0 = 0xFFFFFFFFU,
 
  SMW_SME_WHV_OPTION0_SME_WHV_OPT0 = 0xFFFFFFFFU,
 
  SMW_SETTING_OPTION1_TERS_CTRL0 = 0x7U,
 
  SMW_SETTING_OPTION1_TPGM_CTRL = 0x18U,
 
  SMW_SETTING_OPTION1_TNVS_CTRL = 0xE0U,
 
  SMW_SETTING_OPTION1_TNVH_CTRL = 0x700U,
 
  SMW_SETTING_OPTION1_TPGS_CTRL = 0x3800U,
 
  SMW_SETTING_OPTION1_MAX_ERASE = 0x7FC000U,
 
  SMW_SETTING_OPTION1_MAX_PROG = 0xF800000U,
 
  SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1 = 0xFFFFFFFFU,
 
  SMW_SME_WHV_OPTION1_SME_WHV_OPT1 = 0xFFFFFFFFU,
 
  REPAIR0_0_RDIS0_0 = 0x1U,
 
  REPAIR0_0_RADR0_0 = 0x1FEU,
 
  REPAIR0_1_RDIS0_1 = 0x1U,
 
  REPAIR0_1_RADR0_1 = 0x1FEU,
 
  REPAIR1_0_RDIS1_0 = 0x1U,
 
  REPAIR1_0_RADR1_0 = 0x1FEU,
 
  REPAIR1_1_RDIS1_1 = 0x1U,
 
  REPAIR1_1_RADR1_1 = 0x1FEU,
 
  SMW_HB_SIGNALS_SMW_ARRAY = 0x7U,
 
  SMW_HB_SIGNALS_USER_IFREN1 = 0x8U,
 
  SMW_HB_SIGNALS_USER_PV = 0x10U,
 
  SMW_HB_SIGNALS_USER_EV = 0x20U,
 
  SMW_HB_SIGNALS_USER_IFREN = 0x40U,
 
  SMW_HB_SIGNALS_USER_REDEN = 0x80U,
 
  SMW_HB_SIGNALS_USER_HEM = 0x100U,
 
  BIST_DUMP_CTRL_BIST_DONE = 0x10000U,
 
  BIST_DUMP_CTRL_BIST_FAIL = 0x20000U,
 
  BIST_DUMP_CTRL_DATADUMP = 0x40000U,
 
  BIST_DUMP_CTRL_DATADUMP_TRIG = 0x80000U,
 
  BIST_DUMP_CTRL_DATADUMP_PATT = 0x300000U,
 
  BIST_DUMP_CTRL_DATADUMP_MRGEN = 0x400000U,
 
  BIST_DUMP_CTRL_DATADUMP_MRGTYPE = 0x800000U,
 
  ATX_PIN_CTRL_TM_TO_ATX = 0xFFU,
 
  FAILCNT_FAILCNT = 0xFFFFFFFFU,
 
  PGM_PULSE_CNT0_PGM_CNT0 = 0xFFFFFFFFU,
 
  PGM_PULSE_CNT1_PGM_CNT1 = 0xFFFFFFFFU,
 
  ERS_PULSE_CNT_ERS_CNT0 = 0xFFFFU,
 
  ERS_PULSE_CNT_ERS_CNT1 = 0xFFFF0000U,
 
  MAX_PULSE_CNT_LAST_PCNT = 0x1FFU,
 
  MAX_PULSE_CNT_MAX_ERS_CNT = 0x1FF0000U,
 
  MAX_PULSE_CNT_MAX_PGM_CNT = 0xF8000000U,
 
  PORT_CTRL_BDONE_SEL = 0x3U,
 
  PORT_CTRL_BSDO_SEL = 0xCU
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_2939105B_92A4_4B9F_8147_0850454FD025 */