ctimer/Shift.h

 
#ifndef MCXA153_AE7A3B5B_56CC_4602_942C_53A45C897483
#define MCXA153_AE7A3B5B_56CC_4602_942C_53A45C897483
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
 
namespace mcxa153::chip::ctimer {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace mcxa153::chip::ctimer
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct mcxa153::chip::ctimer::Shift : unsigned int {
  IR_MR0INT = 0U,
 
  IR_MR1INT = 1U,
 
  IR_MR2INT = 2U,
 
  IR_MR3INT = 3U,
 
  IR_CR0INT = 4U,
 
  IR_CR1INT = 5U,
 
  IR_CR2INT = 6U,
 
  IR_CR3INT = 7U,
 
  TCR_CEN = 0U,
 
  TCR_CRST = 1U,
 
  TCR_AGCEN = 4U,
 
  TCR_ATCEN = 5U,
 
  TC_TCVAL = 0U,
 
  PR_PRVAL = 0U,
 
  PC_PCVAL = 0U,
 
  MCR_MR0I = 0U,
 
  MCR_MR0R = 1U,
 
  MCR_MR0S = 2U,
 
  MCR_MR1I = 3U,
 
  MCR_MR1R = 4U,
 
  MCR_MR1S = 5U,
 
  MCR_MR2I = 6U,
 
  MCR_MR2R = 7U,
 
  MCR_MR2S = 8U,
 
  MCR_MR3I = 9U,
 
  MCR_MR3R = 10U,
 
  MCR_MR3S = 11U,
 
  MCR_MR0RL = 24U,
 
  MCR_MR1RL = 25U,
 
  MCR_MR2RL = 26U,
 
  MCR_MR3RL = 27U,
 
  MR_MATCH = 0U,
 
  CCR_CAP0RE = 0U,
 
  CCR_CAP0FE = 1U,
 
  CCR_CAP0I = 2U,
 
  CCR_CAP1RE = 3U,
 
  CCR_CAP1FE = 4U,
 
  CCR_CAP1I = 5U,
 
  CCR_CAP2RE = 6U,
 
  CCR_CAP2FE = 7U,
 
  CCR_CAP2I = 8U,
 
  CCR_CAP3RE = 9U,
 
  CCR_CAP3FE = 10U,
 
  CCR_CAP3I = 11U,
 
  CR_CAP = 0U,
 
  EMR_EM0 = 0U,
 
  EMR_EM1 = 1U,
 
  EMR_EM2 = 2U,
 
  EMR_EM3 = 3U,
 
  EMR_EMC0 = 4U,
 
  EMR_EMC1 = 6U,
 
  EMR_EMC2 = 8U,
 
  EMR_EMC3 = 10U,
 
  CTCR_CTMODE = 0U,
 
  CTCR_CINSEL = 2U,
 
  CTCR_ENCC = 4U,
 
  CTCR_SELCC = 5U,
 
  PWMC_PWMEN0 = 0U,
 
  PWMC_PWMEN1 = 1U,
 
  PWMC_PWMEN2 = 2U,
 
  PWMC_PWMEN3 = 3U,
 
  MSR_MATCH_SHADOW = 0U
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_AE7A3B5B_56CC_4602_942C_53A45C897483 */