mrcc/Shift.h

 
#ifndef MCXA153_47C920EA_AE51_460E_8170_EDF45CFF3A1D
#define MCXA153_47C920EA_AE51_460E_8170_EDF45CFF3A1D
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace mcxa153::chip::mrcc {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace mcxa153::chip::mrcc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct mcxa153::chip::mrcc::Shift : unsigned int {
 
  GLB_RST0_INPUTMUX0 = 0U,
 
  GLB_RST0_I3C0 = 1U,
 
  GLB_RST0_CTIMER0 = 2U,
 
  GLB_RST0_CTIMER1 = 3U,
 
  GLB_RST0_CTIMER2 = 4U,
 
  GLB_RST0_CTIMER3 = 5U,
 
  GLB_RST0_CTIMER4 = 6U,
 
  GLB_RST0_FREQME = 7U,
 
  GLB_RST0_UTICK0 = 8U,
 
  GLB_RST0_DMA = 10U,
 
  GLB_RST0_AOI0 = 11U,
 
  GLB_RST0_CRC0 = 12U,
 
  GLB_RST0_EIM0 = 13U,
 
  GLB_RST0_ERM0 = 14U,
 
  GLB_RST0_AOI1 = 16U,
 
  GLB_RST0_FLEXIO0 = 17U,
 
  GLB_RST0_LPI2C0 = 18U,
 
  GLB_RST0_LPI2C1 = 19U,
 
  GLB_RST0_LPSPI0 = 20U,
 
  GLB_RST0_LPSPI1 = 21U,
 
  GLB_RST0_LPUART0 = 22U,
 
  GLB_RST0_LPUART1 = 23U,
 
  GLB_RST0_LPUART2 = 24U,
 
  GLB_RST0_LPUART3 = 25U,
 
  GLB_RST0_LPUART4 = 26U,
 
  GLB_RST0_USB0 = 27U,
 
  GLB_RST0_QDC0 = 28U,
 
  GLB_RST0_QDC1 = 29U,
 
  GLB_RST0_FLEXPWM0 = 30U,
 
  GLB_RST0_FLEXPWM1 = 31U,
 
  GLB_RST0_SET_DATA = 0U,
 
  GLB_RST0_CLR_DATA = 0U,
 
  GLB_RST1_OSTIMER0 = 0U,
 
  GLB_RST1_ADC0 = 1U,
 
  GLB_RST1_ADC1 = 2U,
 
  GLB_RST1_CMP1 = 4U,
 
  GLB_RST1_DAC0 = 5U,
 
  GLB_RST1_OPAMP0 = 6U,
 
  GLB_RST1_PORT0 = 7U,
 
  GLB_RST1_PORT1 = 8U,
 
  GLB_RST1_PORT2 = 9U,
 
  GLB_RST1_PORT3 = 10U,
 
  GLB_RST1_PORT4 = 11U,
 
  GLB_RST1_FLEXCAN0 = 12U,
 
  GLB_RST1_LPI2C2 = 13U,
 
  GLB_RST1_LPI2C3 = 14U,
 
  GLB_RST1_GPIO0 = 20U,
 
  GLB_RST1_GPIO1 = 21U,
 
  GLB_RST1_GPIO2 = 22U,
 
  GLB_RST1_GPIO3 = 23U,
 
  GLB_RST1_GPIO4 = 24U,
 
  GLB_RST1_SET_DATA = 0U,
 
  GLB_RST1_CLR_DATA = 0U,
 
  GLB_CC0_INPUTMUX0 = 0U,
 
  GLB_CC0_I3C0 = 1U,
 
  GLB_CC0_CTIMER0 = 2U,
 
  GLB_CC0_CTIMER1 = 3U,
 
  GLB_CC0_CTIMER2 = 4U,
 
  GLB_CC0_CTIMER3 = 5U,
 
  GLB_CC0_CTIMER4 = 6U,
 
  GLB_CC0_FREQME = 7U,
 
  GLB_CC0_UTICK0 = 8U,
 
  GLB_CC0_WWDT0 = 9U,
 
  GLB_CC0_DMA = 10U,
 
  GLB_CC0_AOI0 = 11U,
 
  GLB_CC0_CRC0 = 12U,
 
  GLB_CC0_EIM0 = 13U,
 
  GLB_CC0_ERM0 = 14U,
 
  GLB_CC0_FMC = 15U,
 
  GLB_CC0_AOI1 = 16U,
 
  GLB_CC0_FLEXIO0 = 17U,
 
  GLB_CC0_LPI2C0 = 18U,
 
  GLB_CC0_LPI2C1 = 19U,
 
  GLB_CC0_LPSPI0 = 20U,
 
  GLB_CC0_LPSPI1 = 21U,
 
  GLB_CC0_LPUART0 = 22U,
 
  GLB_CC0_LPUART1 = 23U,
 
  GLB_CC0_LPUART2 = 24U,
 
  GLB_CC0_LPUART3 = 25U,
 
  GLB_CC0_LPUART4 = 26U,
 
  GLB_CC0_USB0 = 27U,
 
  GLB_CC0_QDC0 = 28U,
 
  GLB_CC0_QDC1 = 29U,
 
  GLB_CC0_FLEXPWM0 = 30U,
 
  GLB_CC0_FLEXPWM1 = 31U,
 
  GLB_CC0_SET_DATA = 0U,
 
  GLB_CC0_CLR_DATA = 0U,
 
  GLB_CC1_OSTIMER0 = 0U,
 
  GLB_CC1_ADC0 = 1U,
 
  GLB_CC1_ADC1 = 2U,
 
  GLB_CC1_CMP0 = 3U,
 
  GLB_CC1_CMP1 = 4U,
 
  GLB_CC1_DAC0 = 5U,
 
  GLB_CC1_OPAMP0 = 6U,
 
  GLB_CC1_PORT0 = 7U,
 
  GLB_CC1_PORT1 = 8U,
 
  GLB_CC1_PORT2 = 9U,
 
  GLB_CC1_PORT3 = 10U,
 
  GLB_CC1_PORT4 = 11U,
 
  GLB_CC1_FLEXCAN0 = 12U,
 
  GLB_CC1_LPI2C2 = 13U,
 
  GLB_CC1_LPI2C3 = 14U,
 
  GLB_CC1_RAMA = 18U,
 
  GLB_CC1_RAMB = 19U,
 
  GLB_CC1_GPIO0 = 20U,
 
  GLB_CC1_GPIO1 = 21U,
 
  GLB_CC1_GPIO2 = 22U,
 
  GLB_CC1_GPIO3 = 23U,
 
  GLB_CC1_GPIO4 = 24U,
 
  GLB_CC1_ROMC = 25U,
 
  GLB_CC_SET_DATA = 0U,
 
  GLB_CC_CLR_DATA = 0U,
 
  GLB_ACC0_INPUTMUX0 = 0U,
 
  GLB_ACC0_I3C0 = 1U,
 
  GLB_ACC0_CTIMER0 = 2U,
 
  GLB_ACC0_CTIMER1 = 3U,
 
  GLB_ACC0_CTIMER2 = 4U,
 
  GLB_ACC0_CTIMER3 = 5U,
 
  GLB_ACC0_CTIMER4 = 6U,
 
  GLB_ACC0_FREQME = 7U,
 
  GLB_ACC0_UTICK0 = 8U,
 
  GLB_ACC0_WWDT0 = 9U,
 
  GLB_ACC0_DMA = 10U,
 
  GLB_ACC0_AOI0 = 11U,
 
  GLB_ACC0_CRC0 = 12U,
 
  GLB_ACC0_EIM0 = 13U,
 
  GLB_ACC0_ERM0 = 14U,
 
  GLB_ACC0_FMC = 15U,
 
  GLB_ACC0_AOI1 = 16U,
 
  GLB_ACC0_FLEXIO0 = 17U,
 
  GLB_ACC0_LPI2C0 = 18U,
 
  GLB_ACC0_LPI2C1 = 19U,
 
  GLB_ACC0_LPSPI0 = 20U,
 
  GLB_ACC0_LPSPI1 = 21U,
 
  GLB_ACC0_LPUART0 = 22U,
 
  GLB_ACC0_LPUART1 = 23U,
 
  GLB_ACC0_LPUART2 = 24U,
 
  GLB_ACC0_LPUART3 = 25U,
 
  GLB_ACC0_LPUART4 = 26U,
 
  GLB_ACC0_USB0 = 27U,
 
  GLB_ACC0_QDC0 = 28U,
 
  GLB_ACC0_QDC1 = 29U,
 
  GLB_ACC0_FLEXPWM0 = 30U,
 
  GLB_ACC0_FLEXPWM1 = 31U,
 
  GLB_ACC1_OSTIMER0 = 0U,
 
  GLB_ACC1_ADC0 = 1U,
 
  GLB_ACC1_ADC1 = 2U,
 
  GLB_ACC1_CMP0 = 3U,
 
  GLB_ACC1_CMP1 = 4U,
 
  GLB_ACC1_DAC0 = 5U,
 
  GLB_ACC1_OPAMP0 = 6U,
 
  GLB_ACC1_PORT0 = 7U,
 
  GLB_ACC1_PORT1 = 8U,
 
  GLB_ACC1_PORT2 = 9U,
 
  GLB_ACC1_PORT3 = 10U,
 
  GLB_ACC1_PORT4 = 11U,
 
  GLB_ACC1_FLEXCAN0 = 12U,
 
  GLB_ACC1_LPI2C2 = 13U,
 
  GLB_ACC1_LPI2C3 = 14U,
 
  GLB_ACC1_RAMA = 18U,
 
  GLB_ACC1_RAMB = 19U,
 
  GLB_ACC1_GPIO0 = 20U,
 
  GLB_ACC1_GPIO1 = 21U,
 
  GLB_ACC1_GPIO2 = 22U,
 
  GLB_ACC1_GPIO3 = 23U,
 
  GLB_ACC1_GPIO4 = 24U,
 
  GLB_ACC1_ROMC = 25U,
 
  I3C0_FCLK_CLKSEL_MUX = 0U,
 
  I3C0_FCLK_CLKDIV_DIV = 0U,
 
  I3C0_FCLK_CLKDIV_RESET = 29U,
 
  I3C0_FCLK_CLKDIV_HALT = 30U,
 
  I3C0_FCLK_CLKDIV_UNSTAB = 31U,
 
  CTIMER0_CLKSEL_MUX = 0U,
 
  CTIMER0_CLKDIV_DIV = 0U,
 
  CTIMER0_CLKDIV_RESET = 29U,
 
  CTIMER0_CLKDIV_HALT = 30U,
 
  CTIMER0_CLKDIV_UNSTAB = 31U,
 
  CTIMER1_CLKSEL_MUX = 0U,
 
  CTIMER1_CLKDIV_DIV = 0U,
 
  CTIMER1_CLKDIV_RESET = 29U,
 
  CTIMER1_CLKDIV_HALT = 30U,
 
  CTIMER1_CLKDIV_UNSTAB = 31U,
 
  CTIMER2_CLKSEL_MUX = 0U,
 
  CTIMER2_CLKDIV_DIV = 0U,
 
  CTIMER2_CLKDIV_RESET = 29U,
 
  CTIMER2_CLKDIV_HALT = 30U,
 
  CTIMER2_CLKDIV_UNSTAB = 31U,
 
  CTIMER3_CLKSEL_MUX = 0U,
 
  CTIMER3_CLKDIV_DIV = 0U,
 
  CTIMER3_CLKDIV_RESET = 29U,
 
  CTIMER3_CLKDIV_HALT = 30U,
 
  CTIMER3_CLKDIV_UNSTAB = 31U,
 
  CTIMER4_CLKSEL_MUX = 0U,
 
  CTIMER4_CLKDIV_DIV = 0U,
 
  CTIMER4_CLKDIV_RESET = 29U,
 
  CTIMER4_CLKDIV_HALT = 30U,
 
  CTIMER4_CLKDIV_UNSTAB = 31U,
 
  WWDT0_CLKDIV_DIV = 0U,
 
  WWDT0_CLKDIV_RESET = 29U,
 
  WWDT0_CLKDIV_HALT = 30U,
 
  WWDT0_CLKDIV_UNSTAB = 31U,
 
  FLEXIO0_CLKSEL_MUX = 0U,
 
  FLEXIO0_CLKDIV_DIV = 0U,
 
  FLEXIO0_CLKDIV_RESET = 29U,
 
  FLEXIO0_CLKDIV_HALT = 30U,
 
  FLEXIO0_CLKDIV_UNSTAB = 31U,
 
  LPI2C0_CLKSEL_MUX = 0U,
 
  LPI2C0_CLKDIV_DIV = 0U,
 
  LPI2C0_CLKDIV_RESET = 29U,
 
  LPI2C0_CLKDIV_HALT = 30U,
 
  LPI2C0_CLKDIV_UNSTAB = 31U,
 
  LPI2C1_CLKSEL_MUX = 0U,
 
  LPI2C1_CLKDIV_DIV = 0U,
 
  LPI2C1_CLKDIV_RESET = 29U,
 
  LPI2C1_CLKDIV_HALT = 30U,
 
  LPI2C1_CLKDIV_UNSTAB = 31U,
 
  LPSPI0_CLKSEL_MUX = 0U,
 
  LPSPI0_CLKDIV_DIV = 0U,
 
  LPSPI0_CLKDIV_RESET = 29U,
 
  LPSPI0_CLKDIV_HALT = 30U,
 
  LPSPI0_CLKDIV_UNSTAB = 31U,
 
  LPSPI1_CLKSEL_MUX = 0U,
 
  LPSPI1_CLKDIV_DIV = 0U,
 
  LPSPI1_CLKDIV_RESET = 29U,
 
  LPSPI1_CLKDIV_HALT = 30U,
 
  LPSPI1_CLKDIV_UNSTAB = 31U,
 
  LPUART0_CLKSEL_MUX = 0U,
 
  LPUART0_CLKDIV_DIV = 0U,
 
  LPUART0_CLKDIV_RESET = 29U,
 
  LPUART0_CLKDIV_HALT = 30U,
 
  LPUART0_CLKDIV_UNSTAB = 31U,
 
  LPUART1_CLKSEL_MUX = 0U,
 
  LPUART1_CLKDIV_DIV = 0U,
 
  LPUART1_CLKDIV_RESET = 29U,
 
  LPUART1_CLKDIV_HALT = 30U,
 
  LPUART1_CLKDIV_UNSTAB = 31U,
 
  LPUART2_CLKSEL_MUX = 0U,
 
  LPUART2_CLKDIV_DIV = 0U,
 
  LPUART2_CLKDIV_RESET = 29U,
 
  LPUART2_CLKDIV_HALT = 30U,
 
  LPUART2_CLKDIV_UNSTAB = 31U,
 
  LPUART3_CLKSEL_MUX = 0U,
 
  LPUART3_CLKDIV_DIV = 0U,
 
  LPUART3_CLKDIV_RESET = 29U,
 
  LPUART3_CLKDIV_HALT = 30U,
 
  LPUART3_CLKDIV_UNSTAB = 31U,
 
  LPUART4_CLKSEL_MUX = 0U,
 
  LPUART4_CLKDIV_DIV = 0U,
 
  LPUART4_CLKDIV_RESET = 29U,
 
  LPUART4_CLKDIV_HALT = 30U,
 
  LPUART4_CLKDIV_UNSTAB = 31U,
 
  USB0_CLKSEL_MUX = 0U,
 
  LPTMR0_CLKSEL_MUX = 0U,
 
  LPTMR0_CLKDIV_DIV = 0U,
 
  LPTMR0_CLKDIV_RESET = 29U,
 
  LPTMR0_CLKDIV_HALT = 30U,
 
  LPTMR0_CLKDIV_UNSTAB = 31U,
 
  OSTIMER0_CLKSEL_MUX = 0U,
 
  ADC0_CLKSEL_MUX = 0U,
 
  ADC0_CLKDIV_DIV = 0U,
 
  ADC0_CLKDIV_RESET = 29U,
 
  ADC0_CLKDIV_HALT = 30U,
 
  ADC0_CLKDIV_UNSTAB = 31U,
 
  ADC1_CLKSEL_MUX = 0U,
 
  ADC1_CLKDIV_DIV = 0U,
 
  ADC1_CLKDIV_RESET = 29U,
 
  ADC1_CLKDIV_HALT = 30U,
 
  ADC1_CLKDIV_UNSTAB = 31U,
 
  CMP0_FUNC_CLKDIV_DIV = 0U,
 
  CMP0_FUNC_CLKDIV_RESET = 29U,
 
  CMP0_FUNC_CLKDIV_HALT = 30U,
 
  CMP0_FUNC_CLKDIV_UNSTAB = 31U,
 
  CMP0_RR_CLKSEL_MUX = 0U,
 
  CMP0_RR_CLKDIV_DIV = 0U,
 
  CMP0_RR_CLKDIV_RESET = 29U,
 
  CMP0_RR_CLKDIV_HALT = 30U,
 
  CMP0_RR_CLKDIV_UNSTAB = 31U,
 
  CMP1_FUNC_CLKDIV_DIV = 0U,
 
  CMP1_FUNC_CLKDIV_RESET = 29U,
 
  CMP1_FUNC_CLKDIV_HALT = 30U,
 
  CMP1_FUNC_CLKDIV_UNSTAB = 31U,
 
  CMP1_RR_CLKSEL_MUX = 0U,
 
  CMP1_RR_CLKDIV_DIV = 0U,
 
  CMP1_RR_CLKDIV_RESET = 29U,
 
  CMP1_RR_CLKDIV_HALT = 30U,
 
  CMP1_RR_CLKDIV_UNSTAB = 31U,
 
  DAC0_CLKSEL_MUX = 0U,
 
  DAC0_CLKDIV_DIV = 0U,
 
  DAC0_CLKDIV_RESET = 29U,
 
  DAC0_CLKDIV_HALT = 30U,
 
  DAC0_CLKDIV_UNSTAB = 31U,
 
  FLEXCAN0_CLKSEL_MUX = 0U,
 
  FLEXCAN0_CLKDIV_DIV = 0U,
 
  FLEXCAN0_CLKDIV_RESET = 29U,
 
  FLEXCAN0_CLKDIV_HALT = 30U,
 
  FLEXCAN0_CLKDIV_UNSTAB = 31U,
 
  LPI2C2_CLKSEL_MUX = 0U,
 
  LPI2C2_CLKDIV_DIV = 0U,
 
  LPI2C2_CLKDIV_RESET = 29U,
 
  LPI2C2_CLKDIV_HALT = 30U,
 
  LPI2C2_CLKDIV_UNSTAB = 31U,
 
  LPI2C3_CLKSEL_MUX = 0U,
 
  LPI2C3_CLKDIV_DIV = 0U,
 
  LPI2C3_CLKDIV_RESET = 29U,
 
  LPI2C3_CLKDIV_HALT = 30U,
 
  LPI2C3_CLKDIV_UNSTAB = 31U,
 
  DBG_TRACE_CLKSEL_MUX = 0U,
 
  DBG_TRACE_CLKDIV_DIV = 0U,
 
  DBG_TRACE_CLKDIV_RESET = 29U,
 
  DBG_TRACE_CLKDIV_HALT = 30U,
 
  DBG_TRACE_CLKDIV_UNSTAB = 31U,
 
  CLKOUT_CLKSEL_MUX = 0U,
 
  CLKOUT_CLKDIV_DIV = 0U,
 
  CLKOUT_CLKDIV_RESET = 29U,
 
  CLKOUT_CLKDIV_HALT = 30U,
 
  CLKOUT_CLKDIV_UNSTAB = 31U,
 
  SYSTICK_CLKSEL_MUX = 0U,
 
  SYSTICK_CLKDIV_DIV = 0U,
 
  SYSTICK_CLKDIV_RESET = 29U,
 
  SYSTICK_CLKDIV_HALT = 30U,
 
  SYSTICK_CLKDIV_UNSTAB = 31U,
 
  FRO_HF_DIV_CLKDIV_DIV = 0U,
 
  FRO_HF_DIV_CLKDIV_UNSTAB = 31U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_47C920EA_AE51_460E_8170_EDF45CFF3A1D */