Multi-Timer

Counter/Timer 1 Reset Control.

Counter/Timer 1 Reset ControlControls reset state of the Counter/Timer 1 (CTIMER1) peripheral. CTIMER1 provides identical functionality to CTIMER0, enabling multiple independent timing operations and complex timing sequence generation.

計數器/定時器 1 重置控制，獨立計時功能

Identical to CTIMER0:

• Independent 32-bit counter operation
• Separate match registers and PWM outputs
• Individual interrupt sources and configuration

• Can be synchronized with other timers for complex timing

  Coordination:

  // Synchronized reset of multiple timers
  reset_ctrl.assert_reset(Control::CTIMER0);
  reset_ctrl.assert_reset(Control::CTIMER1);
  configure_synchronized_timing();
  reset_ctrl.release_reset(Control::CTIMER0);
  reset_ctrl.release_reset(Control::CTIMER1);