GateName.h

 
#ifndef MCXA153_F69EDF9D_9F4F_4934_A0A7_1B6209076C7D
#define MCXA153_F69EDF9D_9F4F_4934_A0A7_1B6209076C7D
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace mcxa153::chip::clock {
  enum struct GateName : unsigned int;
 
  const uint32 REG_PWM0SUBCTL = 250U;
 
  inline uint32 getGateNameOffset(const GateName _this) {
    return static_cast<uint32>(_this) >> 16;
  }
 
  inline uint32 getGateNameShift(const GateName _this) {
    return static_cast<uint32>(_this) & 0x0000FFFFU;
  }
}  // namespace mcxa153::chip::clock
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct mcxa153::chip::clock::GateName : unsigned int {
  INPUTMUX0   = (0x00000U | (0U)),                
  INPUTMUX    = (0x00000U | (0U)),                
  I3C0        = (0x00000U | (1U)),                
  CTIMER0     = (0x00000U | (2U)),                
  CTIMER1     = (0x00000U | (3U)),                
  CTIMER2     = (0x00000U | (4U)),                
  FREQME      = (0x00000U | (5U)),                
  UTICK0      = (0x00000U | (6U)),                
  WWDT0       = (0x00000U | (7U)),                
  DMA         = (0x00000U | (8U)),                
  AOI0        = (0x00000U | (9U)),                
  CRC         = (0x00000U | (10U)),               
  CRC0        = (0x00000U | (10U)),               
  EIM         = (0x00000U | (11U)),               
  ERM         = (0x00000U | (12U)),               
  LPI2C0      = (0x00000U | (16U)),               
  LPSPI0      = (0x00000U | (17U)),               
  LPSPI1      = (0x00000U | (18U)),               
  LPUART0     = (0x00000U | (19U)),               
  LPUART1     = (0x00000U | (20U)),               
  LPUART2     = (0x00000U | (21U)),               
  USB0        = (0x00000U | (22U)),               
  QDC0        = (0x00000U | (23U)),               
  FLEXPWM0    = (0x00000U | (24U)),               
  OSTIMER0    = (0x00000U | (25U)),               
  ADC0        = (0x00000U | (26U)),               
  CMP0        = (0x00000U | (27U)),               
  CMP1        = (0x00000U | (28U)),               
  PORT0       = (0x00000U | (29U)),               
  PORT1       = (0x00000U | (30U)),               
  PORT2       = (0x00000U | (31U)),               
  PORT3       = ((0x10U << 16U) | (0U)),          
  ATX0        = ((0x10U << 16U) | (1U)),          
  MTR         = ((0x10U << 16U) | (2U)),          
  TCU         = ((0x10U << 16U) | (3U)),          
  EZRAMC_RAMA = ((0x10U << 16U) | (4U)),          
  GPIO0       = ((0x10U << 16U) | (5U)),          
  GPIO1       = ((0x10U << 16U) | (6U)),          
  GPIO2       = ((0x10U << 16U) | (7U)),          
  GPIO3       = ((0x10U << 16U) | (8U)),          
  ROMCP       = ((0x10U << 16U) | (9U)),          
  PWMSM0      = ((REG_PWM0SUBCTL << 16U) | (0U)), 
  PWMSM1      = ((REG_PWM0SUBCTL << 16U) | (1U)), 
  PWMSM2      = ((REG_PWM0SUBCTL << 16U) | (2U)), 
  NOT_AVAIL   = (0xFFFFFFFFU)                     
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_F69EDF9D_9F4F_4934_A0A7_1B6209076C7D */